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JME135-18 PDF预览

JME135-18

更新时间: 2024-11-04 01:12:35
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Chip - double mesa SCRs of reverse blocking high-voltage

JME135-18 数据手册

 浏览型号JME135-18的Datasheet PDF文件第2页浏览型号JME135-18的Datasheet PDF文件第3页 
JIEJIE MICROELECTRONICS CO.,Ltd  
JME135-16/18/20  
Description:  
1) Chip: double mesa SCRs of reverse blocking high-voltage  
2) Chip area: 14.6mm×13.1mm (edge gate thyristor)  
3) Technology: mesa glass passivation technology, multilayer metallization  
technology and non-void welding by vacuum welding technology  
Typical Application:  
Reactive power compensation, solid state relay, power module, etc.  
Absolute Maximum Ratings (Packaged into modules, unless otherwise specified, TC=25)  
Parameter  
Test Conditions  
Symbol  
Tj  
Values  
-40-125  
Unit  
V
Operating junction temperature range  
Repetitive peak off-state voltage  
Repetitive peak reverse voltage  
Average on-state current  
Tj=25  
VDRM  
VRRM  
IT(AV)  
ITSM  
1600/1800/2000  
1600/1800/2000  
135  
Tj=25℃  
TC=80℃  
tp=10ms  
tp=10ms  
V
A
Peak on-state surge current  
I2t value for fusing  
3000  
A
I2t  
45000  
A2s  
VD=2/3VDRM IG=0.3A  
tp=200μs Tj=125℃  
dIG/dt=0.3A/μs  
Critical rate of rise of on-state current  
dI/dt  
150  
A/μs  
Electrical Characteristics (Packaged into modules, unless otherwise specified, TC=25)  
Parameter  
Peak on-state voltage  
Test Conditions  
Symbol  
Values  
Unit  
IT=420A tp=380μs  
VTM  
1.8  
V
VD=VDRM  
TC=25℃  
TC=125℃  
VR=VRRM  
TC=25℃  
TC=125℃  
Repetitive peak off-state current  
Repetitive peak reverse current  
IDRM1  
IDRM2  
100  
25  
μA  
mA  
IRRM1  
IRRM2  
IGT  
100  
25  
μA  
mA  
Triggering gate current  
Latching current  
VD=12V RL=30Ω  
20-150  
300  
250  
2  
mA  
mA  
mA  
V
IG=1.2 IGT  
IL  
Holding current  
IT=1A  
IH  
VD=12V RL=30Ω  
Triggering gate voltage  
VGT  
TEL+86-513-83639777  
-1/3-  
http://www.jjwdz.com  

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