Datasheet > JME135-20

JME135-20

更新时间： 2024-11-04 01:12:35

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描述
Chip - double mesa SCRs of reverse blocking high-voltage

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JME135-20 数据手册

JIEJIE MICROELECTRONICS CO.,Ltd

JME135-16/18/20

Description:

1) Chip: double mesa SCRs of reverse blocking high-voltage

2) Chip area: 14.6mm×13.1mm (edge gate thyristor)

3) Technology: mesa glass passivation technology, multilayer metallization

technology and non-void welding by vacuum welding technology

Typical Application:

Reactive power compensation, solid state relay, power module, etc.

Absolute Maximum Ratings (Packaged into modules, unless otherwise specified, T_C=25℃)

Parameter

Test Conditions

Symbol

T_j

Values

-40-125

Unit

℃

Operating junction temperature range

Repetitive peak off-state voltage

Repetitive peak reverse voltage

Average on-state current

T_j=25℃

V_DRM

V_RRM

I_T(AV)

I_TSM

1600/1800/2000

135

T_j=25℃

T_C=80℃

tp=10ms

Peak on-state surge current

I²t value for fusing

3000

I²t

45000

A²s

V_D=2/3V_DRMI_G=0.3A

tp=200μs T_j=125℃

dI_G/dt=0.3A/μs

Critical rate of rise of on-state current

dI/dt

150

A/μs

Electrical Characteristics (Packaged into modules, unless otherwise specified, T_C=25℃)

Parameter

Peak on-state voltage

Test Conditions

Symbol

Values

Unit

I_T=420A tp=380μs

V_TM

≤1.8

V_D=V_DRM

T_C=25℃

T_C=125℃

V_R=V_RRM

T_C=25℃

T_C=125℃

Repetitive peak off-state current

Repetitive peak reverse current

I_DRM1

I_DRM2

≤100

≤25

μA

I_RRM1

I_RRM2

I_GT

≤100

≤25

μA

Triggering gate current

Latching current

V_D=12V R_L=30Ω

20-150

≤300

≤250

≤2

I_G=1.2 I_GT

I_L

Holding current

I_T=1A

I_H

V_D=12V R_L=30Ω

Triggering gate voltage

V_GT

TEL：+86-513-83639777

-1/3-

http://www.jjwdz.com

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