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ISL54105ACRZ PDF预览

ISL54105ACRZ

更新时间: 2024-09-08 14:42:55
品牌 Logo 应用领域
瑞萨 - RENESAS 商用集成电路
页数 文件大小 规格书
16页 1627K
描述
TMDS Regenerator; QFN72; Temp Range: 0° to 70°

ISL54105ACRZ 技术参数

生命周期:Unknown零件包装代码:QFN
包装说明:HQCCN, LCC72,.39SQ,20针数:72
Reach Compliance Code:compliantHTS代码:8542.39.00.01
Factory Lead Time:7 weeks风险等级:5.28
Is Samacsys:N商用集成电路类型:CONSUMER CIRCUIT
JESD-30 代码:S-PQCC-N72JESD-609代码:e3
长度:10 mm湿度敏感等级:3
功能数量:1端子数量:72
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:HQCCN
封装等效代码:LCC72,.39SQ,20封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG峰值回流温度(摄氏度):260
电源:3.3 V认证状态:Not Qualified
座面最大高度:1 mm子类别:Other Consumer ICs
最大压摆率:405 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V表面贴装:YES
温度等级:COMMERCIAL端子面层:Matte Tin (Sn) - annealed
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:10 mmBase Number Matches:1

ISL54105ACRZ 数据手册

 浏览型号ISL54105ACRZ的Datasheet PDF文件第2页浏览型号ISL54105ACRZ的Datasheet PDF文件第3页浏览型号ISL54105ACRZ的Datasheet PDF文件第4页浏览型号ISL54105ACRZ的Datasheet PDF文件第5页浏览型号ISL54105ACRZ的Datasheet PDF文件第6页浏览型号ISL54105ACRZ的Datasheet PDF文件第7页 
DATASHEET  
Key Features  
ISL54105A  
TMDS Regenerator  
FN6716  
Rev 0.00  
Jun 4, 2008  
The ISL54105A is a high-performance TMDS timing  
regenerator containing a programmable equalizer and a  
clock data recovery (CDR) function for each of the 3 TMDS  
pairs in an HDMI or DVI signal. The TMDS data outputs of  
the ISL54105A are regenerated and perfectly aligned to the  
regenerated TMDS clock signal, creating an extremely  
clean, low-jitter DVI/HDMI signal that can be easily  
decoded by any TMDS receiver.  
Features  
• Clock Data Recovery and Retiming  
• Programmable pre-emphasis on output driver  
• Programmable internal 50100, or high-Z termination  
• Stand-alone or I2C software-controlled operation  
• 72 lead, 10mm x 10mm QFN package  
• Pb-free (RoHS compliant)  
The ISL54105A can be used as a cable extender, to clean  
up a noisy/jittery TMDS source, or to provide a very stable  
TMDS signal to a finicky DVI or HDMI receiver.  
Applications  
• DVI/HDMI extenders  
Televisions/PC monitors/projectors  
Block Diagram  
2
2
TERMINATION  
RXC  
PLL  
TXC  
TX0  
CH0  
CH1  
CH2  
2
D
2
2
2
CDR  
CDR  
CDR  
RX0  
RX1  
RX2  
CK  
D
TERMINATION AND  
EQUALIZATION  
2
2
FIFO  
TX1  
TX2  
CK  
D
CK  
RES_TERM  
RES_BIAS  
BIAS GENERATION  
SDA  
SCL  
7
ACTIVITY  
DETECT  
ADDR  
CONFIGURATION AND CONTROL  
PD  
RESET  
Ordering Information  
PART NUMBER  
TEMP. RANGE (°C)  
0 to +70  
PACKAGE  
72 Ld QFN (Pb-Free)  
PKG. DWG. #  
ISL54105ACRZ  
L72.10x10B  
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%  
matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil  
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.  
FN6716 Rev 0.00  
Jun 4, 2008  
Page 1 of 16  

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