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ISL54106ACRZ PDF预览

ISL54106ACRZ

更新时间： 2024-11-20 21:10:03
品牌 Logo 应用领域
瑞萨 - RENESAS 商用集成电路电视
页数 文件大小 规格书
16页 1236K
描述
IC,TV/VIDEO CIRCUIT,TV INTERFACE CIRCUIT,LLCC,72PIN,PLASTIC

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ISL54106ACRZ 技术参数

是否Rohs认证： 符合生命周期：Transferred
包装说明：QCCN, LCC72,.39SQ,20Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.64商用集成电路类型：CONSUMER CIRCUIT
JESD-30 代码：S-PQCC-N72JESD-609代码：e3
湿度敏感等级：3端子数量：72
最高工作温度：70 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：QCCN
封装等效代码：LCC72,.39SQ,20封装形状：SQUARE
封装形式：CHIP CARRIER电源：3.3 V
认证状态：Not Qualified子类别：Other Consumer ICs
最大压摆率：405 mA表面贴装：YES
温度等级：COMMERCIAL端子面层：Matte Tin (Sn) - annealed
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUADBase Number Matches：1

ISL54106ACRZ 数据手册

 浏览型号ISL54106ACRZ的Datasheet PDF文件第2页浏览型号ISL54106ACRZ的Datasheet PDF文件第3页浏览型号ISL54106ACRZ的Datasheet PDF文件第4页浏览型号ISL54106ACRZ的Datasheet PDF文件第5页浏览型号ISL54106ACRZ的Datasheet PDF文件第6页浏览型号ISL54106ACRZ的Datasheet PDF文件第7页 
ISL54106A  
Key Features  
®
Data Sheet  
June 4, 2008  
FN6717.0  
TMDS Regenerator  
Features  
The ISL54106A is a high-performance TMDS timing  
regenerator containing a programmable equalizer and a  
clock data recovery (CDR) function for each of the 3 TMDS  
pairs in an HDMI or DVI signal. The TMDS data outputs of  
the ISL54106A are regenerated and perfectly aligned to the  
regenerated TMDS clock signal, creating an extremely  
clean, low-jitter DVI/HDMI signal that can be easily  
decoded by any TMDS receiver.  
• Clock Data Recovery and Retiming  
• Programmable pre-emphasis on output driver  
• Programmable internal 50Ω, 100Ω, or high-Z termination  
• Stand-alone or I2C software-controlled operation  
• 72 lead, 10mm x 10mm QFN package  
• Pb-free (RoHS compliant)  
Applications  
The ISL54106A can be used as a cable extender, to clean  
up a noisy/jittery TMDS source, or to provide a very stable  
TMDS signal to a finicky DVI or HDMI receiver.  
• DVI/HDMI extenders  
• Televisions/PC monitors/projectors  
Block Diagram  
2
2
TERMINATION  
RXC  
PLL  
TXC  
TX0  
CH0  
CH1  
CH2  
2
D
2
2
2
CDR  
CDR  
CDR  
RX0  
RX1  
RX2  
CK  
D
TERMINATION AND  
EQUALIZATION  
2
2
FIFO  
TX1  
TX2  
CK  
D
CK  
RES_TERM  
RES_BIAS  
BIAS GENERATION  
SDA  
SCL  
7
ACTIVITY  
DETECT  
ADDR  
CONFIGURATION AND CONTROL  
PD  
RESET  
Ordering Information  
PART NUMBER  
TEMP. RANGE (°C)  
0 to +70  
PACKAGE  
72 Ld QFN (Pb-Free)  
PKG. DWG. #  
L72.10x10B  
ISL54106ACRZ  
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%  
matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil  
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.  
Copyright Intersil Americas Inc. 2008. All Rights Reserved  
All other trademarks mentioned are the property of their respective owners.  
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