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ISL5416KI PDF预览

ISL5416KI

更新时间: 2024-11-19 22:51:43
品牌 Logo 应用领域
英特矽尔 - INTERSIL /
页数 文件大小 规格书
71页 1913K
描述
Four-Channel Wideband Programmable DownConverter

ISL5416KI 数据手册

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ISL5416  
®
Data Sheet  
February 2003  
FN6006.2  
Four-Channel Wideband Programmable  
DownConverter  
Features  
• Up to 95MSPS Input  
The ISL5416 Four-Channel Wideband Programmable Digital  
DownConverter (WPDC) is designed for high dynamic range  
applications such as cellular basestations where the  
processing of multiple channels is required in a small  
physical space. The WPDC combines four channels in a  
single package, each including: an NCO, a digital mixer,  
digital filters, an AGC and a resampling filter.  
• Four Parallel 16-bit Fixed or 17-bit Floating Point Inputs  
• Programmable RF Attenuator/VGA Control  
• 32-Bit Programmable Carrier NCO with > 110dB SFDR  
• 20-bit Internal Data Path  
• Filter Functions  
- Multi-Stage Cascaded-Integrator-Comb (CIC) Filter  
All channels are independently programmable and may be  
updated in real time. Each of the four channels can select  
any of the four digital input buses. Each of the tuners can  
process a W-CDMA channel. Channels may be cascaded or  
polyphased for increased bandwidth. Selectable outputs  
include I samples, Q samples, and AGC gain. Outputs from  
the part are available over the parallel, serial or uP  
interfaces.  
- Two programmable FIR Filters (first up to 32-taps,  
second up to 64-taps)  
- Half Band Interpolation Filter  
- Resampling FIR Filter  
• Overall decimation from 1 to >4096  
• Digital AGC with up to 96dB of Gain Range  
• Up to Four Independent 16-bit Parallel Outputs  
• Serial Output Option  
Ordering Information  
PART  
NUMBER  
TEMP  
o
• 16-bit Parallel µP Interface  
RANGE ( C)  
-40 to 85  
25  
PACKAGE  
PKG. NO  
• 1.8V core, 3.3V I/O Operation  
ISL5416KI  
256 BGA  
V256.17x17  
• Evaluation Board and Configuration Software available  
ISL5416EVAL1  
EVALUATION KIT  
Applications  
• Basestation Receivers: GSM/EDGE, CDMA2000, UMTS.  
Block Diagram  
TEST  
REGISTER  
OUTPUT  
AOUT(15:8)  
I
AOUT(7:0)  
FSYNCA  
OEA  
INPUT  
SELECT  
CLOCK &  
FORMAT  
I
I
I
I
I
AIN(16:0)  
NCO  
MIXER  
CIC  
FIR2  
FILTER  
FIR1  
FILTER  
RESAMPLER  
AGC  
IHBF  
ENIA  
CLKA  
Q
Q
Q
Q
Q
Q
INPUT A  
INPUT B  
CHANNEL O  
CLKO1  
CHANNEL 1  
CHANNEL 2  
CLKO2  
/INTRPT  
INPUT C  
INPUT D  
CHANNEL 3  
RF ATTENUATOR  
VGA CONTROL  
EOUT(15:0)  
RESET  
JTAG  
SYNCHRONIZATION  
µP INTERFACE  
SYNCO SYNCIN1 SYNCIN2  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.  
Copyright © Intersil Americas Inc. 2003. All Rights Reserved  
1
All other trademarks mentioned are the property of their respective owners.  

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