IS66WVE1M16ALL
Advanced Information
1.8V Core Async/Page PSRAM
Overview
The IS66WVE1M16ALL is an integrated memory device containing 16Mbit Pseudo Static Random Access
Memory using a self-refresh DRAM array organized as 1M words by 16 bits. The device includes several
power saving modes : Partial Array Refresh mode where data is retained in a portion of the array and
Deep Power Down mode. Both these modes reduce standby current drain. The die has separate power
rails, VDDQ and VSSQ for the I/O to be run from a separate power supply from the device core.
Features
Asynchronous and page mode interface
Dual voltage rails for optional performance
VDD 1.8V, VDDQ 1.8V
Low Power Feature
Temperature Controlled Refresh
Partial Array Refresh
Deep power-down (DPD) mode
Operating temperature Range
Industrial -40°C~85°C
Page mode read access
Interpage Read access : 70ns
Intrapage Read access : 20ns
Low Power Consumption
Package:
48-ball TFBGA, 48-pin TSOP-I
Asynchronous Operation < 30 mA
Intrapage Read < 18mA
Standby < 80 uA (max.)
Deep power-down (DPD) < 3uA (Typ)
Notes :
1. The 48-pin TSOP-I package option is not yet available. Please contact SRAM marketing at sram@issi.com for
additional information.
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products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services
described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information
and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or
effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to
its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
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www.issi.com - SRAM@issi.com
Rev.00C | November 2010