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IS61S6432N-133TQ PDF预览

IS61S6432N-133TQ

更新时间： 2024-09-12 14:31:23
品牌 Logo 应用领域
美国芯成 - ISSI 静态存储器内存集成电路
页数 文件大小 规格书
16页 132K
描述
Cache SRAM, 64KX32, 5ns, CMOS, PQFP100, TQFP-100

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IS61S6432N-133TQ 技术参数

是否无铅：含铅是否Rohs认证：不符合
生命周期：Obsolete零件包装代码：QFP
包装说明：TQFP-100针数：100
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.88
Is Samacsys：N最长访问时间：5 ns
JESD-30 代码：R-PQFP-G100JESD-609代码：e0
长度：20 mm内存密度：2097152 bit
内存集成电路类型：CACHE SRAM内存宽度：32
功能数量：1端子数量：100
字数：65536 words字数代码：64000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：64KX32
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装形状：RECTANGULAR封装形式：FLATPACK, LOW PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：240
认证状态：Not Qualified座面最大高度：1.6 mm
最大供电电压 (Vsup)：3.63 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
处于峰值回流温度下的最长时间：30宽度：14 mm
Base Number Matches：1

IS61S6432N-133TQ 数据手册

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®
IS61S6432N  
ISSI  
PRELIMINARY INFORMATION  
JANUARY 2002  
64K x 32 SYNCHRONOUS  
PIPELINE STATIC RAM  
DESCRIPTION  
FEATURES  
The ISSI IS61S6432N is a high-speed, low-power  
synchronous static RAM designed to provide a burstable,  
high-performancememory. Itisorganizedas65,536words  
by 32 bits, fabricated with ISSI's advanced CMOS  
technology. The device integrates a 2-bit burst counter,  
high-speed SRAM core, and high-drive capability outputs  
into a single monolithic circuit. All synchronous inputs pass  
through registers controlled by a positive-edge-triggered  
single clock input.  
• Internal self-timed write cycle  
• Individual Byte Write Control and Global Write  
• Clock controlled, registered address, data and  
control  
• Interleaved or linear burst sequence control  
using MODE input  
• Three chip enables for simple depth expansion  
and address pipelining  
Write cycles are internally self-timed and are initiated by the  
rising edge of the clock input. Write cycles can be from one  
to four bytes wide as controlled by the write control inputs.  
• Common data inputs and data outputs  
• Power-down control by ZZ input  
• Single +3.3V power supply  
Separate byte enables allow individual bytes to be written.  
BW1 controls DQ1-DQ8, BW2 controls DQ9-DQ16, BW3  
controls DQ17-DQ24, BW4 controls DQ25-DQ32,  
conditionedbyBWEbeingLOW.ALOWonGWinputwould  
cause all bytes to be written.  
• Two Clock enables and one Clock disable to  
eliminate multiple bank bus contention  
• Control pins mode upon power-up:  
– MODE in interleave burst mode  
Bursts can be initiated with either ADSP (Address Status  
Processor) or ADSC (Address Status Cache Controller)  
input pins. Subsequent burst addresses can be generated  
internally by the IS61S6432N and controlled by the ADV  
(burst address advance) input pin.  
– ZZ in normal operation mode  
These control pins can be connected to GNDQ  
or VCCQ to alter their power-up state  
• Industrial temperature available  
Asynchronous signals include output enable (OE), sleep  
modeinput(ZZ),clock(CLK)andburstmodeinput(MODE).  
A HIGH input on the ZZ pin puts the SRAM in the power-  
down state. When ZZ is pulled LOW (or no connect), the  
SRAM normally operates after three cycles of the wake-up  
period. A LOW input, i.e., GNDQ, on MODE pin selects  
LINEARBurst. AVCCQ (ornoconnect)onMODEpinselects  
INTERLEAVED Burst.  
• JEDEC 100-Pin TQFP and 119 Ball BGA pack-  
ages  
FAST ACCESS TIME  
Symbol  
tKQ  
Parameter  
-133  
5
-5  
5
Unit  
ns  
CLK Access Time  
Cycle Time  
tKC  
7.5  
133  
10  
100  
ns  
—
Frequency  
MHz  
This document contains PRELIMINARY INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best  
possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.  
Integrated Silicon Solution, Inc. • 1-800-379-4774  
1
PRELIMINARY INFORMATION Rev. 00A  
01/31/02  
1234567...16

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IS61SF12832-7.5TQ ISSI

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