Datasheet > IS61SF12832-10TQ

IS61SF12832-10TQ

更新时间： 2024-09-11 22:10:23

品牌	Logo	应用领域
美国芯成 - ISSI		/
页数	文件大小	规格书
16页	114K
描述
128K x 32, 128K x 36 SYNCHRONOUS FLOW-THROUGH STATIC RAM

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IS61SF12832-10TQ 数据手册

IS61SF12832

IS61SF12836

128K x 32, 128K x 36 SYNCHRONOUS

FLOW-THROUGH STATIC RAM

ISSI

APRIL 2001

FEATURES

DESCRIPTION

The ISSI IS61SF12832 and IS61SF12836 are high-speed

synchronous static RAM designed to provide a burstable,

high-performance memory for high speed networking and

communication applications. It is organized as 131,072

words by 32 bits or 36 bits, fabricated with ISSI's advanced

CMOStechnology.Thedeviceintegratesa2-bitburstcounter,

high-speed SRAM core, and high-drive capability outputs into

a single monolithic circuit. All synchronous inputs pass

through registers controlled by a positive-edge-triggered

single clock input.

• Fast access times: 7.5 ns, 8 ns, 8.5 ns, 10 ns,

and 12 ns

• Internal self-timed write cycle

• Individual Byte Write Control and Global Write

• Clock controlled, registered address, data

inputs and control signals

• Pentium™ or linear burst sequence control

using MODE input

• Three chip enables for simple depth expansion

and address pipelining

Write cycles are internally self-timed and are initiated by the

rising edge of the clock input. Write cycles can be from one to

four bytes wide as controlled by the write control inputs.

• Common data inputs and data outputs

Separate byte enables allow individual bytes to be written.

BW1 controls DQa, BW2 controls DQb, BW3 controls DQc,

BW4 controls DQd, conditioned by BWE being LOW. A LOW

on GW input would cause all bytes to be written.

• JEDEC 100-Pin TQFP and

119-pin PBGA package

• Single +3.3V +10%, –5% power supply

• Power-down snooze mode

Bursts can be initiated with either ADSP (Address Status

Processor) or ADSC (Address Status Cache Controller) input

pins.Subsequentburstaddressescanbegeneratedinternally

and controlled by the ADV (burst address advance) input pin.

The mode pin is used to select the burst sequence order,

Linear burst is achieved when this pin is tied LOW. Interleave

burst is achieved when this pin is tied HIGH or left floating.

FAST ACCESS TIME

Symbol

tKQ

Parameter

Clock Access Time

Cycle Time

7.5

8.5

117

100

8.5

Units

tKC

Frequency

MHz

ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

04/17/01

12 3 4 5 6 7...16

中文翻译

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与IS61SF12832-10TQ相关器件

型号	品牌	获取价格	描述	数据表
IS61SF12832-10TQI	ISSI	获取价格	128K x 32, 128K x 36 SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61SF12832-12B	ISSI	获取价格	128K x 32, 128K x 36 SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61SF12832-12TQ	ISSI	获取价格	128K x 32, 128K x 36 SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61SF12832-12TQI	ISSI	获取价格	128K x 32, 128K x 36 SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61SF12832-7.5B	ISSI	获取价格	128K x 32, 128K x 36 SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61SF12832-7.5TQ	ISSI	获取价格	128K x 32, 128K x 36 SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61SF12832-8.5B	ISSI	获取价格	128K x 32, 128K x 36 SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61SF12832-8.5TQ	ISSI	获取价格	128K x 32, 128K x 36 SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61SF12832-8.5TQI	ISSI	获取价格	128K x 32, 128K x 36 SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61SF12832-8B	ISSI	获取价格	128K x 32, 128K x 36 SYNCHRONOUS FLOW-THROUGH STATIC RAM

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