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IS61LV12816-15B PDF预览

IS61LV12816-15B

更新时间: 2024-11-19 22:48:03
品牌 Logo 应用领域
美国芯成 - ISSI /
页数 文件大小 规格书
11页 90K
描述
128K x 16 HIGH-SPEED CMOS STATIC RAM WITH 3.3V SUPPLY

IS61LV12816-15B 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:BGA包装说明:6 X 8 MM, MINI, BGA-48
针数:48Reach Compliance Code:compliant
ECCN代码:3A991.B.2.AHTS代码:8542.32.00.41
风险等级:5.76最长访问时间:15 ns
其他特性:TTL AND CMOS COMPATIBLE INTERFACE LEVELSI/O 类型:COMMON
JESD-30 代码:R-PBGA-B48JESD-609代码:e0
长度:8 mm内存密度:2097152 bit
内存集成电路类型:STANDARD SRAM内存宽度:16
湿度敏感等级:3功能数量:1
端子数量:48字数:131072 words
字数代码:128000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:128KX16输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:LFBGA
封装等效代码:BGA48,6X8,30封装形状:RECTANGULAR
封装形式:GRID ARRAY, LOW PROFILE, FINE PITCH并行/串行:PARALLEL
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3 V
认证状态:Not Qualified座面最大高度:1.35 mm
最大待机电流:0.01 A最小待机电流:3 V
子类别:SRAMs最大压摆率:0.09 mA
最大供电电压 (Vsup):3.63 V最小供电电压 (Vsup):2.97 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:BALL
端子节距:0.75 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:6 mm
Base Number Matches:1

IS61LV12816-15B 数据手册

 浏览型号IS61LV12816-15B的Datasheet PDF文件第2页浏览型号IS61LV12816-15B的Datasheet PDF文件第3页浏览型号IS61LV12816-15B的Datasheet PDF文件第4页浏览型号IS61LV12816-15B的Datasheet PDF文件第5页浏览型号IS61LV12816-15B的Datasheet PDF文件第6页浏览型号IS61LV12816-15B的Datasheet PDF文件第7页 
®
IS61LV12816  
128K x 16 HIGH-SPEED CMOS STATIC RAM  
WITH 3.3V SUPPLY  
ISSI  
NOVEMBER 2000  
FEATURES  
DESCRIPTION  
The ISSI IS61LV12816 is a high-speed, 2,097,152-bit static  
RAM organized as 131,072 words bꢂ 16 bits. It is fabricated  
ꢁsingISSI'shigh-performanceCMOStechnologꢂ. Thishighlꢂ  
reliable process coꢁpled with innovative circꢁit design  
techniqꢁes, ꢂields access times as fast as 8 ns with low power  
consꢁmption.  
• High-speed access time: 8, 10, 12, and 15 ns  
• CMOS low power operation  
• TTL and CMOS compatible interface levels  
• Single 3.3V 10ꢀ power sꢁpplꢂ  
• Fꢁllꢂ static operation: no clock or refresh  
reqꢁired  
When CE is HIGH (deselected), the device assꢁmes a  
standbꢂ mode at which the power dissipation can be redꢁced  
down with CMOS inpꢁt levels.  
• Three state oꢁtpꢁts  
• Data control for ꢁpper and lower bꢂtes  
• Indꢁstrial temperatꢁre available  
EasmemorexpansionisprovidedbsingChipEnableand  
Oꢁtpꢁt Enable inpꢁts, CE and OE. The active LOW Write  
Enable (WE) controls both writing and reading of the memorꢂ.  
A data bꢂte allows Upper Bꢂte (UB) and Lower Bꢂte (LB)  
access.  
The IS61LV12816 is packaged in the JEDEC standard 44-pin  
400-mil SOJ, 44-pin TSOP, 44-pin LQFP, and 48-pin mini  
BGA (6mm x 8mm).  
FUNCTIONAL BLOCK DIAGRAM  
128K x 16  
MEMORY ARRAY  
A0-A16  
DECODER  
VCC  
GND  
I/O0-I/O7  
Lower Byte  
I/O  
DATA  
COLUMN I/O  
CIRCUIT  
I/O8-I/O15  
Upper Byte  
CE  
OE  
WE  
CONTROL  
CIRCUIT  
UB  
LB  
ISSI reserves the right to make changes to its prodꢁcts at anꢂ time withoꢁt notice in order to improve design and sꢁpplꢂ the best possible prodꢁct. We assꢁme no responsibilitꢂ for anꢂ errors  
which maꢂ appear in this pꢁblication. © Copꢂright 2000, Integrated Silicon Solꢁtion, Inc.  
Integrated Silicon Solution, Inc. — 11--880000--337799--44777744  
1
Rev. A  
11/30/00  

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