Datasheet > IS61LPS25632A

IS61LPS25632A

更新时间： 2024-11-13 11:58:59

品牌	Logo	应用领域
美国芯成 - ISSI		/
页数	文件大小	规格书
35页	803K
描述
256K x 36, 256K x 32, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM

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中文翻译

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数据手册

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IS61LPS25632A 数据手册

IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,

IS61VPS51218A, IS61VPS25636A

256K x 36, 256K x 32, 512K x 18

9 Mb SYNCHRONOUS PIPELINED,

SINGLE CYCLE DESELECT STATIC RAM

SEPTEMBER 2012

FEATURES

DESCRIPTION

Theꢀ ISSIꢀ IS61LPS/VPS25636A,ꢀ IS61LPS25632A,ꢀ

IS64LPS25636Aꢀ andꢀ IS61LPS/VPS51218Aꢀ areꢀ high-

speed,ꢀ low-powerꢀ synchronousꢀ staticꢀ RAMs designed

to provide burstable, high-performance memory for com-

municationꢀandꢀnetworkingꢀapplications.ꢀTheꢀIS61LPS/

VPS25636Aꢀ andꢀ IS64LPS25636Aꢀ areꢀ organizedꢀ asꢀ

262,144ꢀ wordsꢀ byꢀ 36ꢀ bits.ꢀ ꢀ Theꢀ IS61LPS25632Aꢀ is

organizedꢀasꢀ262,144ꢀwordsꢀbyꢀ32ꢀbits.ꢀTheꢀIS61LPS/

VPS51218Aꢀisꢀorganizedꢀasꢀ524,288ꢀwordsꢀbyꢀ18ꢀbits.ꢀ

Fabricatedꢀ withꢀ ISSI'sꢀ advancedꢀ CMOSꢀ technology,ꢀ

theꢀdeviceꢀintegratesꢀaꢀ2-bitꢀburstꢀcounter,ꢀhigh-speedꢀ

SRAMꢀcore,ꢀandꢀhigh-driveꢀcapabilityꢀoutputsꢀintoꢀaꢀsingleꢀ

monolithic circuit. All synchronous inputs pass through

registersꢀcontrolledꢀbyꢀaꢀpositive-edge-triggeredꢀsingleꢀ

clock input.

•ꢀ Internalꢀself-timedꢀwriteꢀcycle

•ꢀ IndividualꢀByteꢀWriteꢀControlꢀandꢀGlobalꢀWrite

•ꢀ Clockꢀcontrolled,ꢀregisteredꢀaddress,ꢀdataꢀandꢀ

control

•ꢀ BurstꢀsequenceꢀcontrolꢀusingꢀMODEꢀinputꢀꢀ

•ꢀ Threeꢀchipꢀenableꢀoptionꢀforꢀsimpleꢀdepthꢀex-

pansion and address pipelining

•ꢀ Commonꢀdataꢀinputsꢀandꢀdataꢀoutputs

•ꢀ AutoꢀPower-downꢀduringꢀdeselect

•ꢀ Singleꢀcycleꢀdeselect

•ꢀ SnoozeꢀMODEꢀforꢀreduced-powerꢀstandby

•ꢀ JTAGꢀBoundaryꢀScanꢀforꢀPBGAꢀpackage

•ꢀ PowerꢀSupply

Writeꢀcyclesꢀareꢀinternallyꢀself-timedꢀandꢀareꢀinitiatedꢀbyꢀ

theꢀrisingꢀedgeꢀofꢀtheꢀclockꢀinput.ꢀWriteꢀcyclesꢀcanꢀbeꢀ

one to four bytes wide as controlled by the write control

inputs.

ꢀ LPS:ꢀVdd 3.3V + 5%, Vddq 3.3V/2.5V + 5%

VPS:ꢀVdd 2.5V + 5%, Vddq 2.5V + 5%

Separatebyteenablesallowindividualbytestobewritten.

Theꢀbyteꢀwriteꢀoperationꢀisꢀperformedꢀbyꢀusingꢀtheꢀbyteꢀ

write enable (BWE) input combined with one or more

individual byte write signals (BWx). Inꢀaddition,ꢀGlobalꢀ

Writeꢀ(GW) is available for writing all bytes at one time,

regardless of the byte write controls.

•ꢀ JEDECꢀ100-PinꢀTQFP,ꢀ119-ballꢀPBGA,ꢀandꢀ

165-ballꢀPBGAꢀpackages

•ꢀ Lead-freeꢀavailable

BurstsꢀcanꢀbeꢀinitiatedꢀwithꢀeitherꢀADSP (Address Status

Processor)ꢀorꢀADSC (Address Status Cache Controller)

inputꢀpins.ꢀSubsequentꢀburstꢀaddressesꢀcanꢀbeꢀgener-

ated internally and controlled by the ADV (burst address

advance) input pin.

Theꢀmodeꢀpinꢀisꢀusedꢀtoꢀselectꢀtheꢀburstꢀsequenceꢀor-

der,ꢀLinearꢀburstꢀisꢀachievedꢀwhenꢀthisꢀpinꢀisꢀtiedꢀLOW.ꢀ

InterleaveꢀburstꢀisꢀachievedꢀwhenꢀthisꢀpinꢀisꢀtiedꢀHIGHꢀ

or left ﬂoating.

FAST ACCESS TIME

Symbol

Parameter

250

2.6ꢀ

4ꢀ

200

3.1ꢀ

5ꢀ

166

3.5ꢀ

6ꢀ

Units

tkq

tkc

ꢀ

ClockꢀAccessꢀTimeꢀ

CycleꢀTimeꢀ

ꢀ

Frequencyꢀ

250ꢀ

200ꢀ

166ꢀ

MHz

liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device speciﬁcation before relying on

any published information and before placing orders for products.

Integrated Silicon Solution, Inc.

Rev. L

09/06/12

12 3 4 5 6 7...35

中文翻译

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与IS61LPS25632A相关器件

型号	品牌	获取价格	描述	数据表
IS61LPS25632A-200TQLI	ISSI	获取价格	Cache SRAM, 256KX32, 3.1ns, CMOS, PQFP100, LEAD FREE, TQFP-100
IS61LPS25632D-166B	ISSI	获取价格	Cache SRAM, 256KX32, 3.5ns, CMOS, PBGA119, PLASTIC, BGA-119
IS61LPS25632D-166BI	ISSI	获取价格	Cache SRAM, 256KX32, 3.5ns, CMOS, PBGA119, PLASTIC, BGA-119
IS61LPS25632D-200BI	ISSI	获取价格	Cache SRAM, 256KX32, 3.1ns, CMOS, PBGA119, PLASTIC, BGA-119
IS61LPS25632D-200TQ	ISSI	获取价格	Cache SRAM, 256KX32, 3.1ns, CMOS, PQFP100, TQFP-100
IS61LPS25632D-200TQI	ISSI	获取价格	Cache SRAM, 256KX32, 3.1ns, CMOS, PQFP100, TQFP-100
IS61LPS25632D-225B	ISSI	获取价格	Cache SRAM, 256KX32, 2.8ns, CMOS, PBGA119, PLASTIC, BGA-119
IS61LPS25632D-225TQI	ISSI	获取价格	Cache SRAM, 256KX32, 2.8ns, CMOS, PQFP100, TQFP-100
IS61LPS25632T-225TQI	ISSI	获取价格	Cache SRAM, 256KX32, 2.8ns, CMOS, PQFP100, TQFP-100
IS61LPS25632T-250TQ	ISSI	获取价格	Cache SRAM, 256KX32, 2.6ns, CMOS, PQFP100, TQFP-100

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