Datasheet > IS61LPS25632D-200TQ

IS61LPS25632D-200TQ

更新时间： 2024-09-26 06:39:35

品牌	Logo	应用领域
美国芯成 - ISSI		时钟静态存储器内存集成电路
页数	文件大小	规格书
29页	174K
描述
Cache SRAM, 256KX32, 3.1ns, CMOS, PQFP100, TQFP-100

阅读下载

中文翻译

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

IS61LPS25632D-200TQ 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	TQFP-100	针数：	100
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.88
最长访问时间：	3.1 ns	其他特性：	PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)：	200 MHz	I/O 类型：	COMMON
JESD-30 代码：	R-PQFP-G100	JESD-609代码：	e0
长度：	20 mm	内存密度：	8388608 bit
内存集成电路类型：	CACHE SRAM	内存宽度：	32
功能数量：	1	端子数量：	100
字数：	262144 words	字数代码：	256000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	256KX32
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	LQFP	封装等效代码：	QFP100,.63X.87
封装形状：	RECTANGULAR	封装形式：	FLATPACK, LOW PROFILE
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	240
电源：	2.5/3.3,3.3 V	认证状态：	Not Qualified
座面最大高度：	1.6 mm	最小待机电流：	3.14 V
子类别：	SRAMs	最大供电电压 (Vsup)：	3.465 V
最小供电电压 (Vsup)：	3.135 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	30
宽度：	14 mm

IS61LPS25632D-200TQ 数据手册

浏览型号IS61LPS25632D-200TQ的Datasheet PDF文件第2页

浏览型号IS61LPS25632D-200TQ的Datasheet PDF文件第3页

浏览型号IS61LPS25632D-200TQ的Datasheet PDF文件第4页

浏览型号IS61LPS25632D-200TQ的Datasheet PDF文件第5页

浏览型号IS61LPS25632D-200TQ的Datasheet PDF文件第6页

浏览型号IS61LPS25632D-200TQ的Datasheet PDF文件第7页

IS61LPS25632T/D/J

IS61LPS25636T/D/J

IS61LPS51218T/DJ

ISSI

256K x 32, 256K x 36, 512K x 18

SYNCHRONOUS PIPELINED,

APRIL 2003

SINGLE-CYCLE DESELECT STATIC RAM

DESCRIPTION

FEATURES

The ISSI IS61LPS25632T/D/J,IS61LPS25636T/D/J,and

IS61LPS51218T/D/J are high-speed, low-power synchro-

nous static RAMs designed to provide burstable, high-

performance memory for communication and networking

applications. The IS61LPS25632T/D/J is organized as

262,144 words by 32 bits and the IS61LPS25636T/D/J is

organizedas262,144wordsby36bits.TheIS61LPS51218T/

D/J is organized as 524,288 words by 18 bits. Fabricated

with ISSI's advanced CMOS technology, the device inte-

grates a 2-bit burst counter, high-speed SRAM core, and

high-drivecapabilityoutputsintoasinglemonolithiccircuit.

Allsynchronousinputspassthroughregisterscontrolledby

a positive-edge-triggered single clock input.

• Internal self-timed write cycle

• Individual Byte Write Control and Global Write

• Clock controlled, registered address, data and

control

• Linear burst sequence control using MODE

input

•

Three chip enable option for simple depth

expansion and address pipelining

• Common data inputs and data outputs

• JEDEC 100-Pin TQFP and

119-pin PBGA package

Writecyclesareinternallyself-timedandareinitiatedbythe

risingedgeoftheclockinput.Writecyclescanbeonetofour

bytes wide as controlled by the write control inputs.

• Power Supply

+3.3V V^DD

Separate byte enables allow individual bytes to be written.

Bytewriteoperationisperformedbyusingbytewriteenable

(BWE). Input combined with one or more individual byte

write signals (BWx). In addition, Global Write (GW) is

available for writing all bytes at one time, regardless of the

byte write controls.

+3.3V or 2.5 VDDQ (I/O)

• Auto Power-down during deselect

• Single cycle deselect

• Snooze MODE for reduced-power standby

• JTAG Boundary Scan for PBGA package

• T Version (three chips selects)

• D Version (two chips selects)

• J Version (PBGA Package with JTAG)

Bursts can be initiated with either ADSP (Address Status

Processor) or ADSC (Address Status Cache Controller)

input pins. Subsequent burst addresses can be generated

internally and controlled by the ADV (burst address ad-

vance) input pin.

The mode pin is used to select the burst sequence order,

Linear burst is achieved when this pin is tied LOW. Inter-

leave burst is achieved when this pin is tied HIGH or left

floating.

FAST ACCESS TIME

Symbol

tKQ

Parameter

-250

2.6

-225

2.8

-200

3.1

-166

3.5

Units

Clock Access Time

Cycle Time

tKC

4.4

Frequency

250

225

200

166

MHz

without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to

obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

Rev. A

04/01/03

12 3 4 5 6 7...29

中文翻译

下载PDF

与IS61LPS25632D-200TQ相关器件

型号	品牌	获取价格	描述	数据表
IS61LPS25632D-200TQI	ISSI	获取价格	Cache SRAM, 256KX32, 3.1ns, CMOS, PQFP100, TQFP-100
IS61LPS25632D-225B	ISSI	获取价格	Cache SRAM, 256KX32, 2.8ns, CMOS, PBGA119, PLASTIC, BGA-119
IS61LPS25632D-225TQI	ISSI	获取价格	Cache SRAM, 256KX32, 2.8ns, CMOS, PQFP100, TQFP-100
IS61LPS25632T-225TQI	ISSI	获取价格	Cache SRAM, 256KX32, 2.8ns, CMOS, PQFP100, TQFP-100
IS61LPS25632T-250TQ	ISSI	获取价格	Cache SRAM, 256KX32, 2.6ns, CMOS, PQFP100, TQFP-100
IS61LPS25632T-5TQI	ISSI	获取价格	Cache SRAM, 256KX32, 5ns, CMOS, PQFP100, TQFP-100
IS61LPS25636A	ISSI	获取价格	256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM
IS61LPS25636A-166TQL	ISSI	获取价格	Cache SRAM, 256KX36, 3.8ns, CMOS, PQFP100, LEAD FREE, TQFP-100
IS61LPS25636A-200B2	ISSI	获取价格	256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM
IS61LPS25636A-200B2I	ISSI	获取价格	256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM

与IS61LPS25632D-200TQ相关文章

SK海力士量产12层HBM3E，容量高达36GB
2024-09-27

11
意法半导体传感器驱动Sphere，开启沉浸式电影新时代
2024-09-27

14
摩尔斯微电子在美国约书亚树国家公园测试 Wi-Fi HaLow
2024-09-18

81
贸泽上架Tallysman TW5386智能GNSS天线
2024-09-18

72

产品中心

服务支持

精选活动

关于我们

帮助中心

IS61LPS25632D-200TQ

IS61LPS25632D-200TQ 技术参数

IS61LPS25632D-200TQ 数据手册

与IS61LPS25632D-200TQ相关器件

与IS61LPS25632D-200TQ相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

IS61LPS25632D-200TQ

IS61LPS25632D-200TQ 技术参数

IS61LPS25632D-200TQ 数据手册

与IS61LPS25632D-200TQ相关器件

与IS61LPS25632D-200TQ相关文章

您还可以找

您在本页遇到什么问题？