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IS61LPS25636A-200B2LI

更新时间： 2024-09-25 18:07:39
品牌 Logo 应用领域
美国芯成 - ISSI 静态存储器内存集成电路
页数 文件大小 规格书
35页 576K
描述
Cache SRAM, 256KX36, 3.1ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, MS-028, BGA-119

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IS61LPS25636A-200B2LI 技术参数

是否Rohs认证： 符合生命周期：Active
包装说明：HBGA,Reach Compliance Code：compliant
风险等级：5.72最长访问时间：3.1 ns
JESD-30 代码：R-PBGA-B119JESD-609代码：e1
长度：22 mm内存密度：9437184 bit
内存集成电路类型：CACHE SRAM内存宽度：36
功能数量：1端子数量：119
字数：262144 words字数代码：256000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：256KX36
封装主体材料：PLASTIC/EPOXY封装代码：HBGA
封装形状：RECTANGULAR封装形式：GRID ARRAY, HEAT SINK/SLUG
并行/串行：PARALLEL座面最大高度：3.5 mm
最大供电电压 (Vsup)：3.465 V最小供电电压 (Vsup)：3.165 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Silver/Copper (Sn/Ag/Cu)端子形式：BALL
端子节距：1.27 mm端子位置：BOTTOM
宽度：14 mmBase Number Matches：1

IS61LPS25636A-200B2LI 数据手册

 浏览型号IS61LPS25636A-200B2LI的Datasheet PDF文件第2页浏览型号IS61LPS25636A-200B2LI的Datasheet PDF文件第3页浏览型号IS61LPS25636A-200B2LI的Datasheet PDF文件第4页浏览型号IS61LPS25636A-200B2LI的Datasheet PDF文件第5页浏览型号IS61LPS25636A-200B2LI的Datasheet PDF文件第6页浏览型号IS61LPS25636A-200B2LI的Datasheet PDF文件第7页 
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,  
IS61VPS51218A, IS61VPS25636A  
256K x 36, 256K x 32, 512K x 18  
9 Mb SYNCHRONOUS PIPELINED,  
SINgLE CYCLE DESELECT STATIC RAM  
JANUARY 2014  
FEATURES  
DESCRIPTION  
Theꢀ ISSIꢀ IS61LPS/VPS25636A,ꢀ IS61LPS25632A,ꢀ  
IS64LPS25636Aꢀ andꢀ IS61LPS/VPS51218Aꢀ areꢀ high-  
speed,ꢀ low-powerꢀ synchronousꢀ staticꢀ RAMs designed  
to provide burstable, high-performance memory for com-  
municationꢀandꢀnetworkingꢀapplications.ꢀTheꢀIS61LPS/  
VPS25636Aꢀ andꢀ IS64LPS25636Aꢀ areꢀ organizedꢀ asꢀ  
262,144ꢀ wordsꢀ byꢀ 36ꢀ bits.ꢀ ꢀ Theꢀ IS61LPS25632Aꢀ is  
organizedꢀasꢀ262,144ꢀwordsꢀbyꢀ32ꢀbits.ꢀTheꢀIS61LPS/  
VPS51218Aꢀisꢀorganizedꢀasꢀ524,288ꢀwordsꢀbyꢀ18ꢀbits.ꢀ  
Fabricatedꢀ withꢀ ISSI'sꢀ advancedꢀ CMOSꢀ technology,ꢀ  
theꢀdeviceꢀintegratesꢀaꢀ2-bitꢀburstꢀcounter,ꢀhigh-speedꢀ  
SRAMꢀcore,ꢀandꢀhigh-driveꢀcapabilityꢀoutputsꢀintoꢀaꢀsingleꢀ  
monolithic circuit. All synchronous inputs pass through  
registersꢀcontrolledꢀbyꢀaꢀpositive-edge-triggeredꢀsingleꢀ  
clock input.  
•ꢀ Internalꢀself-timedꢀwriteꢀcycle  
•ꢀ IndividualꢀByteꢀWriteꢀControlꢀandꢀGlobalꢀWrite  
•ꢀ Clockꢀcontrolled,ꢀregisteredꢀaddress,ꢀdataꢀandꢀ  
control  
•ꢀ BurstꢀsequenceꢀcontrolꢀusingꢀMODEꢀinputꢀꢀ  
•ꢀ Threeꢀchipꢀenableꢀoptionꢀforꢀsimpleꢀdepthꢀex-  
pansion and address pipelining  
•ꢀ Commonꢀdataꢀinputsꢀandꢀdataꢀoutputs  
•ꢀ AutoꢀPower-downꢀduringꢀdeselect  
•ꢀ Singleꢀcycleꢀdeselect  
•ꢀ SnoozeꢀMODEꢀforꢀreduced-powerꢀstandby  
•ꢀ JTAGꢀBoundaryꢀScanꢀforꢀBGAꢀpackage  
•ꢀ PowerꢀSupply  
Writeꢀcyclesꢀareꢀinternallyꢀself-timedꢀandꢀareꢀinitiatedꢀbyꢀ  
theꢀrisingꢀedgeꢀofꢀtheꢀclockꢀinput.ꢀWriteꢀcyclesꢀcanꢀbeꢀ  
one to four bytes wide as controlled by the write control  
inputs.  
ꢀ LPS:ꢀVdd 3.3V + 5%, Vddq 3.3V/2.5V + 5%  
VPS:ꢀVdd 2.5V + 5%, Vddq 2.5V + 5%  
Separatebyteenablesallowindividualbytestobewritten.  
Theꢀbyteꢀwriteꢀoperationꢀisꢀperformedꢀbyꢀusingꢀtheꢀbyteꢀ  
write enable (BWE) input combined with one or more  
individual byte write signals (BWx). Inꢀaddition,ꢀGlobalꢀ  
Writeꢀ(GW) is available for writing all bytes at one time,  
regardless of the byte write controls.  
•ꢀ JEDECꢀ100-PinꢀQFP,ꢀ119-ballꢀBGA,ꢀandꢀ165-  
ballꢀBGAꢀpackages  
•ꢀ Lead-freeꢀavailable  
BurstsꢀcanꢀbeꢀinitiatedꢀwithꢀeitherꢀADSP (Address Status  
Processor)ꢀorꢀADSC (Address Status Cache Controller)  
inputꢀpins.ꢀSubsequentꢀburstꢀaddressesꢀcanꢀbeꢀgener-  
ated internally and controlled by the ADV (burst address  
advance) input pin.  
Theꢀmodeꢀpinꢀisꢀusedꢀtoꢀselectꢀtheꢀburstꢀsequenceꢀor-  
der,ꢀLinearꢀburstꢀisꢀachievedꢀwhenꢀthisꢀpinꢀisꢀtiedꢀLOW.ꢀ  
InterleaveꢀburstꢀisꢀachievedꢀwhenꢀthisꢀpinꢀisꢀtiedꢀHIGHꢀ  
or left floating.  
FAST ACCESS TIME  
Symbol  
Parameter  
250  
2.6ꢀ  
4ꢀ  
200  
3.1ꢀ  
5ꢀ  
166  
3.5ꢀ  
6ꢀ  
Units  
ns  
tkq  
tkc  
ꢀ
ClockꢀAccessꢀTimeꢀ  
CycleꢀTimeꢀ  
ns  
ꢀ
Frequencyꢀ  
250ꢀ  
200ꢀ  
166ꢀ  
MHz  
Copyright © 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no  
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on  
any published information and before placing orders for products.  
Integrated Silicon Solution, Inc.  
1
Rev. M  
01/14/14  
1234567...35

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与IS61LPS25636A-200B2LI相关器件

型号 品牌 获取价格 描述 数据表
IS61LPS25636A-200B3 ISSI

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 		256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM
IS61LPS25636A-200B3I ISSI

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 		256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM
IS61LPS25636A-200B3I-TR ISSI

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 		IC SRAM 9M PARALLEL 165TFBGA
IS61LPS25636A-200B3LI ISSI

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 		Cache SRAM, 256KX36, 3.1ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, LEAD FREE, PLASTIC, BGA
IS61LPS25636A-200B3LI-TR ISSI

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 		IC SRAM 9M PARALLEL 165TFBGA
IS61LPS25636A-200TQ ISSI

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 		256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM
IS61LPS25636A-200TQ2I ISSI

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 		256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM
IS61LPS25636A-200TQ2I-TR ISSI

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 		IC SRAM 9M PARALLEL 100TQFP
IS61LPS25636A-200TQ2LI ISSI

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 		暂无描述
IS61LPS25636A-200TQ2LI-TR ISSI

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 		IC SRAM 9M PARALLEL 100TQFP

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