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IS46TR16256AL-187FBLA1 PDF预览

IS46TR16256AL-187FBLA1

更新时间： 2024-10-28 21:11:47
品牌 Logo 应用领域
美国芯成 - ISSI 动态存储器双倍数据速率内存集成电路
页数 文件大小 规格书
81页 2881K
描述
DDR DRAM, 256MX16, 0.3ns, CMOS, PBGA96, 9 X 13 MM, 0.80 MM PITCH, LEAD FREE, FBGA-96

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IS46TR16256AL-187FBLA1 技术参数

生命周期：Obsolete零件包装代码：BGA
包装说明：TFBGA,针数：96
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.32.00.36风险等级：5.63
访问模式：MULTI BANK PAGE BURST最长访问时间：0.3 ns
其他特性：AUTO/SELF REFRESHJESD-30 代码：R-PBGA-B96
长度：13 mm内存密度：4294967296 bit
内存集成电路类型：DDR DRAM内存宽度：16
功能数量：1端口数量：1
端子数量：96字数：268435456 words
字数代码：256000000工作模式：SYNCHRONOUS
组织：256MX16封装主体材料：PLASTIC/EPOXY
封装代码：TFBGA封装形状：RECTANGULAR
封装形式：GRID ARRAY, THIN PROFILE, FINE PITCH座面最大高度：1.2 mm
自我刷新：YES最大供电电压 (Vsup)：1.45 V
最小供电电压 (Vsup)：1.283 V标称供电电压 (Vsup)：1.35 V
表面贴装：YES技术：CMOS
端子形式：BALL端子节距：0.8 mm
端子位置：BOTTOM宽度：9 mm
Base Number Matches：1

IS46TR16256AL-187FBLA1 数据手册

 浏览型号IS46TR16256AL-187FBLA1的Datasheet PDF文件第2页浏览型号IS46TR16256AL-187FBLA1的Datasheet PDF文件第3页浏览型号IS46TR16256AL-187FBLA1的Datasheet PDF文件第4页浏览型号IS46TR16256AL-187FBLA1的Datasheet PDF文件第5页浏览型号IS46TR16256AL-187FBLA1的Datasheet PDF文件第6页浏览型号IS46TR16256AL-187FBLA1的Datasheet PDF文件第7页 
IS43/46TR16256A, IS43/46TR16256AL,  
IS43/46TR85120A, IS43/46TR85120AL  
512Mx8, 256Mx16 4Gb DDR3 SDRAM  
ADVANCED INFORMATION  
DECEMBER 2012  
FEATURES  
•
Standard Voltage: VDD and VDDQ = 1.5V ± 0.075V  
Low Voltage (L): VDD and VDDQ = 1.35V + 0.1V, -0.067V  
•
Refresh Interval:  
7.8 us (8192 cycles/64 ms) Tc= -40°C to 85°C  
3.9 us (8192 cycles/32 ms) Tc= 85°C to 105°C  
•
High speed data transfer rates with system  
frequency up to 933 MHz  
•
•
•
Partial Array Self Refresh  
•
•
•
•
•
8 internal banks for concurrent operation  
8n-Bit pre-fetch architecture  
Asynchronous RESET pin  
TDQS (Termination Data Strobe) supported (x8  
only)  
Programmable CAS Latency  
Programmable Additive Latency: 0, CL-1,CL-2  
•
•
•
•
•
OCD (Off-Chip Driver Impedance Adjustment)  
Dynamic ODT (On-Die Termination)  
Driver strength : RZQ/7, RZQ/6 (RZQ = 240 ©)  
Write Leveling  
Programmable CAS WRITE latency (CWL) based  
on tCK  
•
•
Programmable Burst Length: 4 and 8  
Programmable Burst Sequence: Sequential or  
Interleave  
Operating temperature:  
Commercial (TC = 0°C to +95°C)  
Industrial (TC = -40°C to +95°C)  
Automotive, A1 (TC = -40°C to +95°C)  
Automotive, A2 (TC = -40°C to +105°C)  
•
•
•
BL switch on the fly  
Auto Self Refresh(ASR)  
Self Refresh Temperature(SRT)  
ADDRESS TABLE  
Parameter  
OPTIONS  
512Mx8  
A0-A15  
A0-A9  
BA0-2  
1KB  
256Mx16  
A0-A14  
A0-A9  
BA0-2  
2KB  
•
Configuration:  
Row Addressing  
Column Addressing  
Bank Addressing  
512Mx8  
256Mx16  
•
Package:  
Page size  
Auto Precharge  
Addressing  
96-ball FBGA (9mm x 13mm) for x16  
78-ball FBGA (9mm x 10.5mm) for x8  
A10/AP  
A10/AP  
BL switch on the fly  
A12/BC#  
A12/BC#  
SPEED BIN  
Speed Option  
187F  
15H  
125K  
107M  
Units  
JEDEC Speed Grade  
DDR3-1066F  
DDR3-1333H  
DDR3-1600K  
DDR3-1866M  
CL-nRCD-nRP  
tRCD,tRP(min)  
Note:  
7-7-7  
13.125  
9-9-9  
13.125  
11-11-11  
13.125  
13-13-13  
13.91  
tCK  
ns  
Faster speed options are backward compatible to slower speed options.  
Copyright © 2012 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time  
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised  
to obtain the latest version of this device specification before relying on any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product  
can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use  
in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:  
a.) the risk of injury or damage has been minimized;  
b.) the user assume all such risks; and  
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances  
Integrated Silicon Solution, Inc. – www.issi.com –  
1
Rev. 00A  
12/5/2012  
1234567...81

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