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IS46TR16640BL-125JBLA2 PDF预览

IS46TR16640BL-125JBLA2

更新时间: 2024-11-23 22:58:15
品牌 Logo 应用领域
美国芯成 - ISSI 动态存储器双倍数据速率内存集成电路
页数 文件大小 规格书
87页 4343K
描述
IC DRAM 1G PARALLEL 96TWBGA

IS46TR16640BL-125JBLA2 技术参数

是否Rohs认证: 符合生命周期:End Of Life
包装说明:TFBGA,Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.32.00.32
Factory Lead Time:10 weeks风险等级:5.59
访问模式:MULTI BANK PAGE BURST其他特性:AUTO/SELF REFRESH
JESD-30 代码:R-PBGA-B96JESD-609代码:e1
长度:13 mm内存密度:1073741824 bit
内存集成电路类型:DDR DRAM内存宽度:16
功能数量:1端口数量:1
端子数量:96字数:67108864 words
字数代码:64000000工作模式:SYNCHRONOUS
组织:64MX16封装主体材料:PLASTIC/EPOXY
封装代码:TFBGA封装形状:RECTANGULAR
封装形式:GRID ARRAY, THIN PROFILE, FINE PITCH峰值回流温度(摄氏度):NOT SPECIFIED
座面最大高度:1.2 mm自我刷新:YES
最大供电电压 (Vsup):1.45 V最小供电电压 (Vsup):1.283 V
标称供电电压 (Vsup):1.35 V表面贴装:YES
技术:CMOS端子面层:Tin/Silver/Copper (Sn/Ag/Cu)
端子形式:BALL端子节距:0.8 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:9 mmBase Number Matches:1

IS46TR16640BL-125JBLA2 数据手册

 浏览型号IS46TR16640BL-125JBLA2的Datasheet PDF文件第2页浏览型号IS46TR16640BL-125JBLA2的Datasheet PDF文件第3页浏览型号IS46TR16640BL-125JBLA2的Datasheet PDF文件第4页浏览型号IS46TR16640BL-125JBLA2的Datasheet PDF文件第5页浏览型号IS46TR16640BL-125JBLA2的Datasheet PDF文件第6页浏览型号IS46TR16640BL-125JBLA2的Datasheet PDF文件第7页 
IS43/46TR16640B, IS43/46TR16640BL  
IS43/46TR81280B, IS43/46TR81280BL  
128MX8, 64MX16 1Gb DDR3 SDRAM  
FEBRUARY 2018  
FEATURES  
Standard Voltage: VDD and VDDQ = 1.5V ± 0.075V  
Refresh Interval:  
7.8 us (8192 cycles/64 ms) Tc= -40°C to 85°C  
3.9 us (8192 cycles/32 ms) Tc= 85°C to 105°C  
Low Voltage (L): VDD and VDDQ = 1.35V + 0.1V, -0.067V  
- Backward compatible to 1.5V  
High speed data transfer rates with system  
frequency up to 1066 MHz  
Partial Array Self Refresh  
Asynchronous RESET pin  
8 internal banks for concurrent operation  
8n-bit pre-fetch architecture  
TDQS (Termination Data Strobe) supported (x8  
only)  
OCD (Off-Chip Driver Impedance Adjustment)  
Dynamic ODT (On-Die Termination)  
Driver strength : RZQ/7, RZQ/6 (RZQ = 240 )  
Write Leveling  
Programmable CAS Latency  
Programmable Additive Latency: 0, CL-1,CL-2  
Programmable CAS WRITE latency (CWL) based  
on tCK  
Programmable Burst Length: 4 and 8  
Up to 200 MHz in DLL off mode  
Operating temperature:  
Programmable Burst Sequence: Sequential or  
Interleave  
Commercial (TC = 0°C to +95°C)  
Industrial (TC = -40°C to +95°C)  
Automotive, A1 (TC = -40°C to +95°C)  
Automotive, A2 (TC = -40°C to +105°C)  
BL switch on the fly  
Auto Self Refresh(ASR)  
Self Refresh Temperature(SRT)  
OPTIONS  
ADDRESS TABLE  
Parameter  
Configuration:  
128Mx8  
64Mx16  
128Mx8  
A0-A13  
A0-A9  
64Mx16  
A0-A12  
A0-A9  
Row Addressing  
Column Addressing  
Bank Addressing  
Page size  
Package:  
96-ball BGA (9mm x 13mm) for x16  
78-ball BGA (8mm x 10.5mm) for x8  
BA0-2  
BA0-2  
1KB  
2KB  
Auto Precharge Addressing  
BL switch on the fly  
A10/AP  
A12/BC#  
A10/AP  
A12/BC#  
SPEED BIN  
Speed Option  
15G  
125K  
125J  
107M  
093N  
Units  
JEDEC Speed Grade  
DDR3-1333G  
DDR3-1600K  
DDR3-1600J  
DDR3-1866M  
DDR3-2133N  
CL-nRCD-nRP  
tRCD,tRP(min)  
8-8-8  
12.0  
11-11-11  
13.75  
10-10-10  
12.5  
13-13-13  
13.91  
14-14-14  
13.09  
tCK  
ns  
Note: Faster speed options may be backward compatible to slower speed options. Refer to timing tables (8.3)  
Copyright © 2018 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time  
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised  
to obtain the latest version of this device specification before relying on any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product  
can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use  
in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:  
a.) the risk of injury or damage has been minimized;  
b.) the user assume all such risks; and  
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances  
Integrated Silicon Solution, Inc. www.issi.com –  
1
Rev. I1  
02/14/2018  

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