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IS46TR16640ED-125KBLA3 PDF预览

IS46TR16640ED-125KBLA3

更新时间: 2024-10-28 15:42:19
品牌 Logo 应用领域
美国芯成 - ISSI 动态存储器双倍数据速率内存集成电路
页数 文件大小 规格书
74页 3393K
描述
DDR DRAM, 64MX16, CMOS, PBGA96, FBGA-96

IS46TR16640ED-125KBLA3 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:TFBGA,Reach Compliance Code:unknown
ECCN代码:EAR99Factory Lead Time:10 weeks
风险等级:5.61访问模式:MULTI BANK PAGE BURST
其他特性:PROGRAMMABLE CAS LATENCY; AUTO/SELF REFRESHJESD-30 代码:R-PBGA-B96
JESD-609代码:e1长度:13 mm
内存密度:1073741824 bit内存集成电路类型:DDR DRAM
内存宽度:16湿度敏感等级:3
功能数量:1端口数量:1
端子数量:96字数:67108864 words
字数代码:64000000工作模式:SYNCHRONOUS
最高工作温度:125 °C最低工作温度:-40 °C
组织:64MX16封装主体材料:PLASTIC/EPOXY
封装代码:TFBGA封装形状:RECTANGULAR
封装形式:GRID ARRAY, THIN PROFILE, FINE PITCH峰值回流温度(摄氏度):260
座面最大高度:1.2 mm自我刷新:YES
最大供电电压 (Vsup):1.575 V最小供电电压 (Vsup):1.425 V
标称供电电压 (Vsup):1.5 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子面层:Tin/Silver/Copper (Sn/Ag/Cu)端子形式:BALL
端子节距:0.8 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:10宽度:9 mm
Base Number Matches:1

IS46TR16640ED-125KBLA3 数据手册

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IS43/46TR16640ED  
IS43/46TR81280ED  
128MX8, 64MX16 1Gb DDR3 SDRAM WITH ECC  
Preliminary Information  
AUGUST 2016  
FEATURES  
Standard Voltage: VDD and VDDQ = 1.5V ± 0.075V  
Refresh Interval:  
7.8 μs (8192 cycles/64 ms) Tc= -40°C to 85°C  
3.9 μs (8192 cycles/32 ms) Tc= 85°C to 105°C  
1.95 μs (8192 cycles/16ms)Tc=105°C to 125°C  
High speed data transfer rates with system  
frequency up to 800 MHz  
8 internal banks for concurrent operation  
8n-bit pre-fetch architecture  
Partial Array Self Refresh  
Asynchronous RESET pin  
Programmable CAS Latency  
TDQS (Termination Data Strobe) supported (x8  
only)  
Programmable Additive Latency: 0, CL-1,CL-2  
Programmable CAS WRITE latency (CWL) based  
on tCK  
OCD (Off-Chip Driver Impedance Adjustment)  
Dynamic ODT (On-Die Termination)  
Driver strength : RZQ/7, RZQ/6 (RZQ = 240 )  
Write Leveling  
Programmable Burst Length: 4 and 8  
Programmable Burst Sequence: Sequential or  
Interleave  
BL switch on the fly  
Operating temperature:  
Automotive, A1 (TC = -40°C to +95°C)  
Automotive, A2 (TC = -40°C to +105°C)  
Automotive, A3 (TC= -40°C to +125°C)  
Auto Self Refresh(ASR)  
Self Refresh Temperature(SRT)  
ECC  
Single bit error correction (per 64-bits)  
ADDRESS TABLE  
Parameter  
Restrictions on Burst Length and Data Mask  
128Mx8  
A0-A13  
A0-A9  
64Mx16  
A0-A12  
A0-A9  
Row Addressing  
Column Addressing  
Bank Addressing  
Page size  
OPTIONS  
Configuration:  
BA0-2  
BA0-2  
128Mx8  
64Mx16  
1KB  
2KB  
Auto Precharge Addressing  
BL switch on the fly  
A10/AP  
A12/BC#  
A10/AP  
A12/BC#  
Package:  
96-ball FBGA (9mm x 13mm) for x16  
78-ball FBGA (8mm x 10.5mm) for x8  
SPEED BIN  
Speed Option  
15H  
125K  
Units  
JEDEC Speed Grade  
DDR3-1333H  
DDR3-1600K  
CL-nRCD-nRP  
tRCD,tRP(min)  
9-9-9  
13.5  
11-11-11  
13.75  
tCK  
ns  
Note: Faster speed options may be backward compatible to slower speed options. Refer to timing tables (8.3)  
Copyright © 2016 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time  
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised  
to obtain the latest version of this device specification before relying on any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product  
can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use  
in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:  
a.) the risk of injury or damage has been minimized;  
b.) the user assume all such risks; and  
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances  
Integrated Silicon Solution, Inc. www.issi.com –  
1
Rev. 0B  
08/08/2016  

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