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IS25C02-3PLA3 PDF预览

IS25C02-3PLA3

更新时间: 2024-11-08 04:06:59
品牌 Logo 应用领域
美国芯成 - ISSI 可编程只读存储器
页数 文件大小 规格书
17页 134K
描述
2K-BIT/4K-BIT SPI SERIAL ELECTRICALLY ERASABLE PROM

IS25C02-3PLA3 数据手册

 浏览型号IS25C02-3PLA3的Datasheet PDF文件第2页浏览型号IS25C02-3PLA3的Datasheet PDF文件第3页浏览型号IS25C02-3PLA3的Datasheet PDF文件第4页浏览型号IS25C02-3PLA3的Datasheet PDF文件第5页浏览型号IS25C02-3PLA3的Datasheet PDF文件第6页浏览型号IS25C02-3PLA3的Datasheet PDF文件第7页 
®
IS25C02  
IS25C04  
2K-BIT/4K-BIT SPI SERIAL  
ELECTRICALLY ERASABLE PROM  
ISSI  
PreliminaryInformation  
January2006  
FEATURES  
DESCRIPTION  
TheIS25C02andIS25C04areelectricallyerasable  
PROM devices that use the Serial Peripheral Interface  
(SPI) for communications. The IS25C02 is 2Kbit  
(256x 8) and the IS25C04 is 4Kbit (512x 8). The  
IS25C02/04EEPROMsareofferedinawideoperating  
voltage range of 1.8V to 5.5V to be compatible with  
most application voltages. ISSI designed the IS25C02/  
04 to be an efficient SPI EEPROM solution. The  
• SerialPeripheralInterface(SPI)Compatible  
— Supports SPI Modes 0 (0,0) and 3 (1,1)  
• Low-voltageOperation  
— Vcc = 1.8V to 5.5V  
• LowpowerCMOS  
— Active current less than 3.0 mA (2.5V)  
— Standby current less than 1 µA (2.5V)  
• Block Write Protection  
devices are packaged in 8-pin PDIP, 8-pin SOIC, and 8-  
pin TSSOP.  
— Protect 1/4, 1/2, or Entire Array  
• 16 byte page write mode  
— Partial page writes allowed  
• 10 MHz Clock Rate (5V)  
• Self timed write cycles  
— 5 ms max. @ 2.5V  
• High-reliability  
— Endurance: 1 million cycles per byte  
— Data retention: 100 years  
• 8-pin PDIP, 8-pin SOIC, and 8-pin TSSOP packages  
areavailable  
The functional features of the IS25C02/04 allow them to  
beamongthemostadvancedserialnon-volatilememo-  
ries available. Each device has a Chip-Select (CS) pin,  
and a 3-wire interface of Serial Data In (SI), Serial Data  
Out (SO), and Serial Clock (SCK). While the 3-wire  
interfaceoftheIS25C02/04providesforhigh-speed  
access, a HOLD pin allows the memories to ignore the  
interface in a suspended state; later the HOLD pin re-  
activates communication without re-initializing the serial  
sequence. A Status Register facilitates a flexible write  
• Lead-freeavailable  
protectionmechanism,andadevice-readybit(RDY).  
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time  
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to  
obtain the latest version of this device specification before relying on any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
1
Preliminary Information Rev. 00F  
12/22/05  

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