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IRFC11N50AB PDF预览

IRFC11N50AB

更新时间: 2024-11-06 14:42:51
品牌 Logo 应用领域
威世 - VISHAY /
页数 文件大小 规格书
3页 69K
描述
Power Field-Effect Transistor, 500V, 0.52ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, 0.165 X 0.248 INCH, DIE-3

IRFC11N50AB 技术参数

生命周期:Active零件包装代码:DIE
包装说明:UNCASED CHIP, R-XUUC-N2针数:3
Reach Compliance Code:unknownFactory Lead Time:9 weeks
风险等级:5.76Is Samacsys:N
配置:SINGLE WITH BUILT-IN DIODE最小漏源击穿电压:500 V
最大漏源导通电阻:0.52 ΩFET 技术:METAL-OXIDE SEMICONDUCTOR
JESD-30 代码:R-XUUC-N2元件数量:1
端子数量:2工作模式:ENHANCEMENT MODE
最高工作温度:150 °C封装主体材料:UNSPECIFIED
封装形状:RECTANGULAR封装形式:UNCASED CHIP
极性/信道类型:N-CHANNEL认证状态:Not Qualified
表面贴装:YES端子形式:NO LEAD
端子位置:UPPER晶体管元件材料:SILICON
Base Number Matches:1

IRFC11N50AB 数据手册

 浏览型号IRFC11N50AB的Datasheet PDF文件第2页浏览型号IRFC11N50AB的Datasheet PDF文件第3页 
PD - 94737  
IRFC11N50AB  
HEXFET® Power MOSFET Die in Wafer Form  
l 100% Tested at Probe   
l Available in Chip Pack, Unsawn Wafer  
Sawn on Film ‚  
D
500V  
RDS(on) = 0.52  
(max.)  
G
5" Wafer  
l Ultra Low On-Resistance  
S
Key Electrical Characteristics (Packaged Part)  
Parameter  
V(BR)DSS  
RDS(on)  
VGS(th)  
IDSS  
Description  
Drain-to-Source Breakdown Voltage  
Static Drain-to-Source On-Resistance  
Gate Threshold Voltage  
Min.  
500V  
–––  
2.0V  
–––  
Typ.  
–––  
–––  
–––  
–––  
Max. Test Conditions  
VGS = 0V, ID = 250µA  
VGS = 10V, ID = 6.6A  
–––  
0.52  
4.0V  
VDS = VGS, ID = 250µA  
VDS= 500V, VGS=0V, TJ=25°C  
VGS = ±30V  
Drain-to-Source Leakage Current  
Gate-to-Source Leakage Current  
Operating Junction and  
25µA  
IGSS  
±100nA  
TJ  
-55°C to 150°C Max.  
TSTG  
Storage Temperature Range  
Mechanical Data  
Nominal Backmetal Composition, (Thickness)  
Nominal Front Metal Composition, (Thickness)  
Dimensions  
Cr- Ni - Ag, (1kA°-2kA°-2.5kA°)  
Al with 1% Si (3.0µm)  
0.165" x 0.248"  
Wafer Diameter  
125 mm, with 100 flat  
425 µm  
Wafer Thickness, Tolerance  
Relevant Die Mechanical Dwg. Number  
Minimum Street Width  
01-5342  
0.084 mm  
Reject Ink Dot Size  
0.51 mm diameter minimum  
Recommended Storage Environment  
Store in original container, in dessicated  
nitrogen, with no contamination  
For optimum electrical results, die attach  
temperature should not exceed 300°C  
IRFB11N50A  
Recommended Die Attach Conditions  
Referenced Package Part:  
Die Outline  
Note:  
 The above data sheet is based on IR sample testing under certain predetermined and assumed conditions, and is  
provided for illustration purposes only. Customers are encouraged to perform testing in actual proposed packaged  
and use conditions. IR die products are tested using IR-based quality assurance procedures and are manufac-  
tured using IR’s established processes. Programs for customer-specified testing are available upon request. IR  
has experienced assembly yields of generally 95% or greater for individual die; however, customer’s results may  
vary. Estimates such as those described and set forth in this data sheet for semiconductor die will vary depending  
on a number of packaging, handling, use and other factors. Sold die may not perform on an equivalent basis to  
standard package products and are therefore offered with a limited warranty as described in IR’s applicable  
standard terms and conditions of sale. All IR die sales are subject to IR’s applicable standard terms and conditions  
of sale, which are available upon request.  
‚ Part number shown is for die in waferform. Contact factory for these other options.  
07/18/03  
Document Number: 90422  
www.vishay.com  
1

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