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IRF7413ZTR PDF预览

IRF7413ZTR

更新时间: 2024-01-18 08:53:02
品牌 Logo 应用领域
英飞凌 - INFINEON /
页数 文件大小 规格书
10页 272K
描述
Control FET for Notebook Processor Power

IRF7413ZTR 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOT包装说明:SMALL OUTLINE, R-PDSO-G8
针数:8Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8541.29.00.95
风险等级:5.64雪崩能效等级(Eas):32 mJ
配置:SINGLE WITH BUILT-IN DIODE最小漏源击穿电压:30 V
最大漏极电流 (ID):13 A最大漏源导通电阻:0.01 Ω
FET 技术:METAL-OXIDE SEMICONDUCTORJESD-30 代码:R-PDSO-G8
JESD-609代码:e3湿度敏感等级:1
元件数量:1端子数量:8
工作模式:ENHANCEMENT MODE封装主体材料:PLASTIC/EPOXY
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260极性/信道类型:N-CHANNEL
最大脉冲漏极电流 (IDM):100 A认证状态:Not Qualified
表面贴装:YES端子面层:MATTE TIN
端子形式:GULL WING端子位置:DUAL
处于峰值回流温度下的最长时间:30晶体管应用:AMPLIFIER
晶体管元件材料:SILICONBase Number Matches:1

IRF7413ZTR 数据手册

 浏览型号IRF7413ZTR的Datasheet PDF文件第4页浏览型号IRF7413ZTR的Datasheet PDF文件第5页浏览型号IRF7413ZTR的Datasheet PDF文件第6页浏览型号IRF7413ZTR的Datasheet PDF文件第7页浏览型号IRF7413ZTR的Datasheet PDF文件第9页浏览型号IRF7413ZTR的Datasheet PDF文件第10页 
IRF7413Z  
Power MOSFET Selection for Non-Isolated DC/DC Converters  
Synchronous FET  
Control FET  
The power loss equation for Q2 is approximated  
by;  
Special attention has been given to the power losses  
in the switching elements of the circuit - Q1 and Q2.  
Power losses in the high side switch Q1, also called  
the Control FET, are impacted by the Rds(on) of the  
MOSFET, but these conduction losses are only about  
one half of the total losses.  
P = P  
+ P + P*  
loss  
conduction  
drive  
output  
P = Irms 2 × Rds(on)  
loss ( )  
Power losses in the control switch Q1 are given  
by;  
+ Q × V × f  
(
)
g
g
Qoss  
Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput  
+
×V × f + Q × V × f  
(
)
in  
rr  
in  
2  
This can be expanded and approximated by;  
*dissipated primarily in Q1.  
P
= I 2 × Rds(on)  
(
)
loss  
rms  
For the synchronous MOSFET Q2, Rds(on) is an im-  
portant characteristic; however, once again the im-  
portance of gate charge must not be overlooked since  
it impacts three critical areas. Under light load the  
MOSFET must still be turned on and off by the con-  
trol IC so the gate drive losses become much more  
significant. Secondly, the output charge Qoss and re-  
verse recovery charge Qrr both generate losses that  
are transfered to Q1 and increase the dissipation in  
that device. Thirdly, gate charge will impact the  
MOSFETs’ susceptibility to Cdv/dt turn on.  
Qgd  
ig  
Qgs2  
ig  
+ I ×  
× V × f + I ×  
× V × f  
in  
in  
+ Q × V × f  
(
)
g
g
Qoss  
+
×V × f  
in  
2
This simplified loss equation includes the terms Qgs2  
The drain of Q2 is connected to the switching node  
of the converter and therefore sees transitions be-  
tween ground and Vin. As Q1 turns on and off there is  
a rate of change of drain voltage dV/dt which is ca-  
pacitively coupled to the gate of Q2 and can induce  
a voltage spike on the gate that is sufficient to turn  
the MOSFET on, resulting in shoot-through current .  
The ratio of Qgd/Qgs1 must be minimized to reduce the  
potential for Cdv/dt turn on.  
and Qoss which are new to Power MOSFET data sheets.  
Qgs2 is a sub element of traditional gate-source  
charge that is included in all MOSFET data sheets.  
The importance of splitting this gate-source charge  
into two sub elements, Qgs1 and Qgs2, can be seen from  
Fig 16.  
Qgs2 indicates the charge that must be supplied by  
the gate driver between the time that the threshold  
voltage has been reached and the time the drain cur-  
rent rises to Idmax at which time the drain voltage be-  
gins to change. Minimizing Qgs2 is a critical factor in  
reducing switching losses in Q1.  
Qoss is the charge that must be supplied to the out-  
put capacitance of the MOSFET during every switch-  
ing cycle. Figure A shows how Qoss is formed by the  
parallel combination of the voltage dependant (non-  
linear) capacitance’s Cds and Cdg when multiplied by  
the power supply input buss voltage.  
Figure A: Qoss Characteristic  
8
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