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IDT72V12165L15TFI PDF预览

IDT72V12165L15TFI

更新时间: 2024-11-09 05:11:59
品牌 Logo 应用领域
艾迪悌 - IDT 存储内存集成电路先进先出芯片时钟
页数 文件大小 规格书
8页 122K
描述
3.3 VOLT MULTIMEDIA FIFO 256 x 16, 512 x 16, 1,024 x 16, 2,048 x 16, and 4,096 x 16

IDT72V12165L15TFI 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:QFP包装说明:10 X 10 MM, PLASTIC, STQFP-64
针数:64Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.32.00.71
风险等级:5.52Is Samacsys:N
最长访问时间:10 ns最大时钟频率 (fCLK):66.7 MHz
周期时间:15 nsJESD-30 代码:S-PQFP-G64
JESD-609代码:e0长度:10 mm
内存密度:8192 bit内存集成电路类型:OTHER FIFO
内存宽度:16湿度敏感等级:3
功能数量:1端子数量:64
字数:512 words字数代码:512
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:512X16
可输出:YES封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装等效代码:QFP64,.66SQ,32
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
并行/串行:PARALLEL峰值回流温度(摄氏度):225
电源:3.3 V认证状态:Not Qualified
座面最大高度:1.6 mm最大待机电流:0.005 A
子类别:FIFOs最大压摆率:0.03 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:10 mm
Base Number Matches:1

IDT72V12165L15TFI 数据手册

 浏览型号IDT72V12165L15TFI的Datasheet PDF文件第2页浏览型号IDT72V12165L15TFI的Datasheet PDF文件第3页浏览型号IDT72V12165L15TFI的Datasheet PDF文件第4页浏览型号IDT72V12165L15TFI的Datasheet PDF文件第5页浏览型号IDT72V12165L15TFI的Datasheet PDF文件第6页浏览型号IDT72V12165L15TFI的Datasheet PDF文件第7页 
3.3 VOLT MULTIMEDIA FIFO  
256 x 16, 512 x 16,  
1,024 x 16, 2,048 x 16,  
and 4,096 x 16  
IDT72V11165, IDT72V12165  
IDT72V13165, IDT72V14165  
IDT72V15165  
FEATURES  
DESCRIPTION  
256 x 16-bit organization array (IDT72V11165)  
512 x 16-bit organization array (IDT72V12165)  
1,024 x 16-bit organization array (IDT72V13165)  
2,048 x 16-bit organization array (IDT72V14165)  
4,096 x 16-bit organization array (IDT72V15165)  
15 ns read/write cycle time  
TheIDT72V11165/72V12165/72V13165/72V14165/72V15165 devices  
areFirst-In,First-Out(FIFO)memorieswithclockedreadandwritecontrols.  
TheseFIFOshave16-bitinputandoutputports. Theinputportiscontrolled  
byafree-runningclock(WCLK),andaninputenablepin(WEN).Dataiswritten  
intotheMultimediaFIFOoneveryclockwhenWENisasserted.Theoutputport  
iscontrolledbyanotherclockpin(RCLK)andanotherenablepin(REN).The  
ReadClock(RCLK)canbetiedtotheWriteClockforsingleclockoperationor  
thetwoclockscanrunasynchronousofoneanotherfordual-clockoperation.  
AnOutputEnablepin(OE)isprovidedonthereadportforthree-statecontrol  
oftheoutput.  
5V input tolerant  
Independent Read and Write Clocks  
Empty/Full and Half-Full flag capability  
Output enable puts output data bus in high-impedance state  
Available in a 64-lead thin quad flatpack (10x10mm and 14x14mm  
TQFP)  
TheseMultimediaFIFOs supportthreefixedflags:EmptyFlag(EF),Full  
Flag (FF), and Half Full Flag (HF).  
Industrial temperature range (–40°C to +85°C)  
FUNCTIONAL BLOCK DIAGRAM  
WCLK  
RCLK  
READ  
CONTROL  
WRITE  
CONTROL  
WEN  
REN  
OE  
FIFO ARRAY  
D0  
- D15  
Q0 - Q15  
Data In  
x16  
Data Out  
x16  
RESET LOGIC  
FLAG OUTPUTS  
EF  
HF  
FF  
RS  
6359 drw01  
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc.  
NOVEMBER 2003  
INDUSTRIAL TEMPERATURE RANGE  
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-6359/2  

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