Datasheet > IDT72V14081

IDT72V14081

更新时间： 2024-11-18 23:01:15

品牌	Logo	应用领域
艾迪悌 - IDT		先进先出芯片
页数	文件大小	规格书
9页	124K
描述
3.3 VOLT MULTIMEDIA FIFO

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中文翻译

获取价格

数据手册

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IDT72V14081 数据手册

3.3 VOLT MULTIMEDIA FIFO

256 x 8, 512 x 8,

1,024 x 8, 2,048 x 8,

and 4,096 x 8

IDT72V10081, IDT72V11081

IDT72V12081, IDT72V13081

IDT72V14081

DESCRIPTION

FEATURES

TheIDT72V10081/72V11081/72V12081/72V13081/72V14081devices

arelow-powerFirst-In,First-Out(FIFO)memorieswithclockedreadandwrite

controls. These devices have a 256, 512, 1,024, 2,048 and 4,096 x 8-bit

memoryarray,respectively.TheseFIFOsareapplicableforawidevarietyof

databufferingneedssuchasgraphicsandinterprocessorcommunication.

These FIFOs have 8-bit input and output ports. The input port is

controlledbya free-runningclock(WCLK)and Write Enable pin(WEN).

Data is writtenintothe Multimedia FIFOoneveryrisingclockedge when

the Write Enable pinis asserted.The outputportis controlledbyanother

clock pin (RCLK) and Read Enable pin (REN). The Read Clock can be

tiedtothe Write Clockforsingle clockoperationorthe twoclocks canrun

asynchronous ofone anotherfordual-clockoperation.AnOutputEnable

pin(OE)is providedonthe readportforthree-state controlofthe output.

The Multimedia FIFOs have two fixed flags, Empty (EF) and Full (FF).

TheseFIFOs arefabricatedusingIDT's submicronCMOStechnology.

• 256 x 8-bit organization array (IDT72V10081)

• 512 x 8-bit organization array (IDT72V11081)

• 1,024 x 8-bit organization array (IDT72V12081)

• 2,048 x 8-bit organization array (IDT72V13081)

• 4,096 x 8-bit organization array (IDT72V14081)

• 15 ns read/write cycle time

• 5V input tolerant

• Independent Read and Write clocks

• Empty and Full Flags signal FIFO status

• Output Enable puts output data bus in high-impedance state

• Available in 32-pin plastic Thin Quad FlatPack (TQFP)

• Industrial temperature range (–40°C to +85°C)

FUNCTIONAL BLOCK DIAGRAM

WCLK

RCLK

READ

CONTROL

WRITE

CONTROL

WEN

REN

FIFO ARRAY

- D

Q0 - Q7

Data In

Data Out

RESET LOGIC

FLAG OUTPUTS

6161 drw01

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.

INDUSTRIAL TEMPERATURE RANGES

NOVEMBER 2003

DSC-6161/2

12 3 4 5 6 7...9

中文翻译

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与IDT72V14081相关器件

型号	品牌	获取价格	描述	数据表
IDT72V14081L15PFGI	IDT	获取价格	FIFO, 4KX8, 10ns, Synchronous, CMOS, PQFP32, PLASTIC, TQFP-32
IDT72V14081L15PFI	IDT	获取价格	3.3 VOLT MULTIMEDIA FIFO
IDT72V14081L15PFI8	IDT	获取价格	FIFO, 4KX8, 10ns, Synchronous, CMOS, PQFP32, PLASTIC, TQFP-32
IDT72V14165	IDT	获取价格	3.3 VOLT MULTIMEDIA FIFO 256 x 16, 512 x 16, 1,024 x 16, 2,048 x 16, and 4,096 x 16
IDT72V14165L15TFGI	IDT	获取价格	FIFO, 2KX16, 10ns, Synchronous, PQFP64, 10 X 10 MM, PLASTIC, STQFP-64
IDT72V14165L15TFI	IDT	获取价格	3.3 VOLT MULTIMEDIA FIFO 256 x 16, 512 x 16, 1,024 x 16, 2,048 x 16, and 4,096 x 16
IDT72V14165L15TFI8	IDT	获取价格	FIFO, 2KX16, 10ns, Synchronous, PQFP64, 10 X 10 MM, PLASTIC, STQFP-64
IDT72V14320	IDT	获取价格	3.3V MULTIMEDIA FIFO 16 BIT V-III, 32 BIT Vx-III FAMILY UP TO 1 Mb DENSITY
IDT72V14320L10PFGI8	IDT	获取价格	FIFO, 1KX32, 6.5ns, Synchronous, CMOS, PQFP128, TQFP-128
IDT72V14320L10PFI	IDT	获取价格	FIFO, 1KX32, 6.5ns, Synchronous, CMOS, PQFP128, TQFP-128

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