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IDT72V14081L15PFI8 PDF预览

IDT72V14081L15PFI8

更新时间: 2024-11-20 08:42:47
品牌 Logo 应用领域
艾迪悌 - IDT 时钟先进先出芯片内存集成电路
页数 文件大小 规格书
9页 124K
描述
FIFO, 4KX8, 10ns, Synchronous, CMOS, PQFP32, PLASTIC, TQFP-32

IDT72V14081L15PFI8 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:PLASTIC, TQFP-32
针数:32Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.32.00.71
风险等级:5.69最长访问时间:10 ns
最大时钟频率 (fCLK):66.7 MHz周期时间:15 ns
JESD-30 代码:S-PQFP-G32JESD-609代码:e0
长度:7 mm内存密度:32768 bit
内存集成电路类型:OTHER FIFO内存宽度:8
湿度敏感等级:3功能数量:1
端子数量:32字数:4096 words
字数代码:4000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:4KX8可输出:YES
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装等效代码:QFP32,.35SQ,32封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE并行/串行:PARALLEL
峰值回流温度(摄氏度):225电源:3.3 V
认证状态:Not Qualified座面最大高度:1.6 mm
最大待机电流:0.005 A子类别:FIFOs
最大压摆率:0.02 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:0.8 mm
端子位置:QUAD处于峰值回流温度下的最长时间:20
宽度:7 mm

IDT72V14081L15PFI8 数据手册

 浏览型号IDT72V14081L15PFI8的Datasheet PDF文件第2页浏览型号IDT72V14081L15PFI8的Datasheet PDF文件第3页浏览型号IDT72V14081L15PFI8的Datasheet PDF文件第4页浏览型号IDT72V14081L15PFI8的Datasheet PDF文件第5页浏览型号IDT72V14081L15PFI8的Datasheet PDF文件第6页浏览型号IDT72V14081L15PFI8的Datasheet PDF文件第7页 
3.3 VOLT MULTIMEDIA FIFO  
256 x 8, 512 x 8,  
1,024 x 8, 2,048 x 8,  
and 4,096 x 8  
IDT72V10081, IDT72V11081  
IDT72V12081, IDT72V13081  
IDT72V14081  
DESCRIPTION  
FEATURES  
TheIDT72V10081/72V11081/72V12081/72V13081/72V14081devices  
arelow-powerFirst-In,First-Out(FIFO)memorieswithclockedreadandwrite  
controls. These devices have a 256, 512, 1,024, 2,048 and 4,096 x 8-bit  
memoryarray,respectively.TheseFIFOsareapplicableforawidevarietyof  
databufferingneedssuchasgraphicsandinterprocessorcommunication.  
These FIFOs have 8-bit input and output ports. The input port is  
controlledbya free-runningclock(WCLK)and Write Enable pin(WEN).  
Data is writtenintothe Multimedia FIFOoneveryrisingclockedge when  
the Write Enable pinis asserted.The outputportis controlledbyanother  
clock pin (RCLK) and Read Enable pin (REN). The Read Clock can be  
tiedtothe Write Clockforsingle clockoperationorthe twoclocks canrun  
asynchronous ofone anotherfordual-clockoperation.AnOutputEnable  
pin(OE)is providedonthe readportforthree-state controlofthe output.  
The Multimedia FIFOs have two fixed flags, Empty (EF) and Full (FF).  
TheseFIFOs arefabricatedusingIDT's submicronCMOStechnology.  
256 x 8-bit organization array (IDT72V10081)  
512 x 8-bit organization array (IDT72V11081)  
1,024 x 8-bit organization array (IDT72V12081)  
2,048 x 8-bit organization array (IDT72V13081)  
4,096 x 8-bit organization array (IDT72V14081)  
15 ns read/write cycle time  
5V input tolerant  
Independent Read and Write clocks  
Empty and Full Flags signal FIFO status  
Output Enable puts output data bus in high-impedance state  
Available in 32-pin plastic Thin Quad FlatPack (TQFP)  
Industrial temperature range (–40°C to +85°C)  
FUNCTIONAL BLOCK DIAGRAM  
WCLK  
RCLK  
READ  
CONTROL  
WRITE  
CONTROL  
WEN  
REN  
OE  
FIFO ARRAY  
D0  
- D  
7
Q0 - Q7  
Data In  
x8  
Data Out  
x8  
RESET LOGIC  
FLAG OUTPUTS  
EF  
FF  
RS  
6161 drw01  
IDTandtheIDTlogoaretrademarksofIntegratedDeviceTechnology,Inc.  
INDUSTRIAL TEMPERATURE RANGES  
NOVEMBER 2003  
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-6161/3  

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