Datasheet > IDT72V14071

IDT72V14071

更新时间： 2024-11-07 05:11:59

品牌	Logo	应用领域
艾迪悌 - IDT		先进先出芯片
页数	文件大小	规格书
10页	151K
描述
3.3 VOLT DUAL MULTIMEDIA FIFO

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中文翻译

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数据手册

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IDT72V14071 数据手册

3.3 VOLT DUAL MULTIMEDIA FIFO

DUAL 256 x 8, DUAL 512 x 8

DUAL 1,024 x 8, DUAL 2,048 x 8

DUAL 4,096 x 8

IDT72V10071,IDT72V11071

IDT72V12071,IDT72V13071

IDT72V14071

FIFOs in a single package with all associated control, data, and flag lines

assignedtoseparatepins.

FEATURES

• Memory organization:

Eachofthe twoFIFOs (designatedFIFOAandFIFOB)has a 8-bitinput

data port (DA0 - DA7, DB0 - DB7) and a 8-bit output data port (QA0 - QA7,

QB0 - QB7). Each input port is controlled by a free-running clock (WCLKA,

WCLKB),andaWriteEnablepin(WENA,WENB).Dataiswrittenintoeachof

thetwoarraysoneveryrisingclockedgeoftheWriteClock(WCLKA,WCLKB)

whentheappropriateWriteEnablepinisasserted.

TheoutputportofeachFIFObankiscontrolledbyitsassociated clockpin

(RCLKA,RCLKB)andReadEnablepin(RENA,RENB).TheReadClockcan

betiedtotheWriteClockforsingleclockoperationorthetwoclocks canrun

asynchronousofoneanotherfordualclockoperation.AnOutputEnablepin

(OEA,OEB)is providedonthe readportofeachFIFOforthree-state output

control.

IDT72V10071

IDT72V11071

IDT72V12071

IDT72V13071

IDT72V14071



Dual 256 x 8

Dual 512 x 8

Dual 1,024 x 8

Dual 2,048 x 8

Dual 4,096 x 8

• Offers optimal combination of large capacity, high speed,

design flexibility and small footprint

• 15 ns read/write cycle time

• 5V input tolerant

• Separate control lines and data lines for each FIFO

• Separate Empty and Full flags for each FIFO

• Enable puts output data lines in high-impedance state

• Space-saving 64-pin plastic Thin Quad Flat Pack (STQFP)

EachofthetwoFIFOshastwofixedflags,Empty(EFA,EFB)andFull(FFA,

FFB).

This FIFOis fabricatedusingIDT's high-performancesubmicronCMOS

technology.

• Industrial temperature range (–40°C to +85°C)

DESCRIPTION

TheIDT72V10071/72V11071/72V12071/72V13071/72V14071aredual

Multimedia FIFOs. The device is functionallyequivalenttotwoindependent

FUNCTIONAL BLOCK DIAGRAM

WCLKA

RCLKA

READ

CONTROL

WRITE

CONTROL

WENA

RENA

OEA

FIFO ARRAY

A0 - DA7

Data In

256 x 8, 512 x 8

1,024 x 8, 2,048 x 8

4,096 x 8

QA0 - QA7

Data Out

RESET LOGIC

FLAG OUTPUTS

RSA

EFA

FFA

WCLKB

RCLKB

READ

CONTROL

WRITE

CONTROL

WENB

RENB

OEB

FIFO ARRAY

256 x 8, 512 x 8

1,024 x 8, 2,048 x 8

4,096 x 8

B0 - DB7

Data In

B0 - QB7

Data Out

RESET LOGIC

FLAG OUTPUTS

6360 drw01

RSB

EFB

FFB

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.

NOVEMBER 2003

INDUSTRIAL TEMPERATURE RANGE



DSC-6360/1

12 3 4 5 6 7...10

中文翻译

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与IDT72V14071相关器件

型号	品牌	获取价格	描述	数据表
IDT72V14071L15	IDT	获取价格	3.3 VOLT DUAL MULTIMEDIA FIFO
IDT72V14071L15TFI	IDT	获取价格	FIFO, 8KX8, 10ns, Synchronous, CMOS, PQFP64, PLASTIC, TQFP-64
IDT72V14071L15TFI8	IDT	获取价格	FIFO, 8KX8, 10ns, Synchronous, CMOS, PQFP64, PLASTIC, TQFP-64
IDT72V14081	IDT	获取价格	3.3 VOLT MULTIMEDIA FIFO
IDT72V14081L15PFGI	IDT	获取价格	FIFO, 4KX8, 10ns, Synchronous, CMOS, PQFP32, PLASTIC, TQFP-32
IDT72V14081L15PFI	IDT	获取价格	3.3 VOLT MULTIMEDIA FIFO
IDT72V14081L15PFI8	IDT	获取价格	FIFO, 4KX8, 10ns, Synchronous, CMOS, PQFP32, PLASTIC, TQFP-32
IDT72V14165	IDT	获取价格	3.3 VOLT MULTIMEDIA FIFO 256 x 16, 512 x 16, 1,024 x 16, 2,048 x 16, and 4,096 x 16
IDT72V14165L15TFGI	IDT	获取价格	FIFO, 2KX16, 10ns, Synchronous, PQFP64, 10 X 10 MM, PLASTIC, STQFP-64
IDT72V14165L15TFI	IDT	获取价格	3.3 VOLT MULTIMEDIA FIFO 256 x 16, 512 x 16, 1,024 x 16, 2,048 x 16, and 4,096 x 16

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