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IDT72V14071L15TFI8 PDF预览

IDT72V14071L15TFI8

更新时间: 2024-11-19 21:09:07
品牌 Logo 应用领域
艾迪悌 - IDT 时钟先进先出芯片内存集成电路
页数 文件大小 规格书
10页 145K
描述
FIFO, 8KX8, 10ns, Synchronous, CMOS, PQFP64, PLASTIC, TQFP-64

IDT72V14071L15TFI8 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:PLASTIC, TQFP-64
针数:64Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.32.00.71
风险等级:5.73最长访问时间:10 ns
最大时钟频率 (fCLK):66.7 MHz周期时间:15 ns
JESD-30 代码:S-PQFP-G64JESD-609代码:e0
长度:10 mm内存密度:65536 bit
内存集成电路类型:OTHER FIFO内存宽度:8
湿度敏感等级:3功能数量:1
端子数量:64字数:8192 words
字数代码:8000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:8KX8可输出:YES
封装主体材料:PLASTIC/EPOXY封装代码:TFQFP
封装等效代码:QFP64,.47SQ,20封装形状:SQUARE
封装形式:FLATPACK, THIN PROFILE, FINE PITCH并行/串行:PARALLEL
峰值回流温度(摄氏度):225电源:3.3 V
认证状态:Not Qualified座面最大高度:1.2 mm
最大待机电流:0.01 A子类别:FIFOs
最大压摆率:0.04 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:10 mmBase Number Matches:1

IDT72V14071L15TFI8 数据手册

 浏览型号IDT72V14071L15TFI8的Datasheet PDF文件第2页浏览型号IDT72V14071L15TFI8的Datasheet PDF文件第3页浏览型号IDT72V14071L15TFI8的Datasheet PDF文件第4页浏览型号IDT72V14071L15TFI8的Datasheet PDF文件第5页浏览型号IDT72V14071L15TFI8的Datasheet PDF文件第6页浏览型号IDT72V14071L15TFI8的Datasheet PDF文件第7页 
3.3 VOLT DUAL MULTIMEDIA FIFO  
DUAL 256 x 8, DUAL 512 x 8  
DUAL 1,024 x 8, DUAL 2,048 x 8  
DUAL 4,096 x 8  
IDT72V10071,IDT72V11071  
IDT72V12071,IDT72V13071  
IDT72V14071  
FIFOs in a single package with all associated control, data, and flag lines  
assignedtoseparatepins.  
FEATURES  
Memory organization:  
Eachofthe twoFIFOs (designatedFIFOAandFIFOB)has a 8-bitinput  
data port (DA0 - DA7, DB0 - DB7) and a 8-bit output data port (QA0 - QA7,  
QB0 - QB7). Each input port is controlled by a free-running clock (WCLKA,  
WCLKB),andaWriteEnablepin(WENA,WENB).Dataiswrittenintoeachof  
thetwoarraysoneveryrisingclockedgeoftheWriteClock(WCLKA,WCLKB)  
whentheappropriateWriteEnablepinisasserted.  
TheoutputportofeachFIFObankiscontrolledbyitsassociated clockpin  
(RCLKA,RCLKB)andReadEnablepin(RENA,RENB).TheReadClockcan  
betiedtotheWriteClockforsingleclockoperationorthetwoclocks canrun  
asynchronousofoneanotherfordualclockoperation.AnOutputEnablepin  
(OEA,OEB)is providedonthe readportofeachFIFOforthree-state output  
control.  
IDT72V10071  
IDT72V11071  
IDT72V12071  
IDT72V13071  
IDT72V14071  
Dual 256 x 8  
Dual 512 x 8  
Dual 1,024 x 8  
Dual 2,048 x 8  
Dual 4,096 x 8  
Offers optimal combination of large capacity, high speed,  
design flexibility and small footprint  
15 ns read/write cycle time  
5V input tolerant  
Separate control lines and data lines for each FIFO  
Separate Empty and Full flags for each FIFO  
Enable puts output data lines in high-impedance state  
Space-saving 64-pin plastic Thin Quad Flat Pack (STQFP)  
EachofthetwoFIFOshastwofixedflags,Empty(EFA,EFB)andFull(FFA,  
FFB).  
This FIFOis fabricatedusingIDT's high-performancesubmicronCMOS  
technology.  
Industrial temperature range (–40°C to +85°C)  
DESCRIPTION  
TheIDT72V10071/72V11071/72V12071/72V13071/72V14071aredual  
Multimedia FIFOs. The device is functionallyequivalenttotwoindependent  
FUNCTIONAL BLOCK DIAGRAM  
WCLKA  
RCLKA  
READ  
CONTROL  
WRITE  
CONTROL  
WENA  
RENA  
OEA  
FIFO ARRAY  
D
A0 - DA7  
Data In  
256 x 8, 512 x 8  
1,024 x 8, 2,048 x 8  
4,096 x 8  
QA0 - QA7  
Data Out  
x8  
x8  
RESET LOGIC  
FLAG OUTPUTS  
RSA  
EFA  
FFA  
WCLKB  
RCLKB  
READ  
CONTROL  
WRITE  
CONTROL  
WENB  
RENB  
OEB  
FIFO ARRAY  
256 x 8, 512 x 8  
1,024 x 8, 2,048 x 8  
4,096 x 8  
D
B0 - DB7  
Data In  
Q
B0 - QB7  
Data Out  
x8  
x8  
RESET LOGIC  
FLAG OUTPUTS  
6360 drw01  
RSB  
EFB  
FFB  
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.  
NOVEMBER 2003  
INDUSTRIAL TEMPERATURE RANGE  
1
2003 Integrated Device Technology, Inc. All rights reserved. Products specifications subject to change without notice.  
DSC-6360/1  

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