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IDT71V65613S166BG8 PDF预览

IDT71V65613S166BG8

更新时间: 2024-09-18 19:50:51
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
26页 558K
描述
ZBT SRAM, 256KX36, 3.5ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119

IDT71V65613S166BG8 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:BGA
包装说明:BGA,针数:119
Reach Compliance Code:compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.68
最长访问时间:3.5 nsJESD-30 代码:R-PBGA-B119
JESD-609代码:e0长度:22 mm
内存密度:9437184 bit内存集成电路类型:ZBT SRAM
内存宽度:36湿度敏感等级:3
功能数量:1端子数量:119
字数:262144 words字数代码:256000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:256KX36
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装形状:RECTANGULAR封装形式:GRID ARRAY
并行/串行:PARALLEL峰值回流温度(摄氏度):225
认证状态:Not Qualified座面最大高度:2.36 mm
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:TIN LEAD端子形式:BALL
端子节距:1.27 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:20宽度:14 mm
Base Number Matches:1

IDT71V65613S166BG8 数据手册

 浏览型号IDT71V65613S166BG8的Datasheet PDF文件第2页浏览型号IDT71V65613S166BG8的Datasheet PDF文件第3页浏览型号IDT71V65613S166BG8的Datasheet PDF文件第4页浏览型号IDT71V65613S166BG8的Datasheet PDF文件第5页浏览型号IDT71V65613S166BG8的Datasheet PDF文件第6页浏览型号IDT71V65613S166BG8的Datasheet PDF文件第7页 
256K x 36, 512K x 18  
3.3VSynchronousZBT™SRAMs  
3.3V I/O, Burst Counter  
PipelinedOutputs  
Preliminary  
IDT71V65613  
IDT71V65813  
Features  
AddressandcontrolsignalsareappliedtotheSRAMduringoneclock  
cycle,andtwocycleslatertheassociateddatacycleoccurs,beitreadorwrite.  
TheIDT71V65613/5813containdataI/O,addressandcontrolsignal  
registers.Outputenableistheonlyasynchronoussignalandcanbeused  
todisabletheoutputsatanygiventime.  
AClockEnable(CEN)pinallowsoperationoftheIDT71V65613/5813  
to be suspended as long as necessary. All synchronous inputs are  
ignoredwhen(CEN)ishighandtheinternaldeviceregisterswillholdtheir  
previous values.  
There are three chip enable pins (CE1, CE2, CE2) that allow the  
user to deselect the device when desired. If any one of these three are  
not asserted when ADV/LD is low, no new memory operation can be  
initiated. However, any pending data transfers (reads or writes) will be  
completed.Thedatabuswilltri-statetwocyclesafterchipisdeselectedor  
awriteisinitiated.  
The IDT71V65613/5813 have an on-chip burst counter. In the burst  
mode,theIDT71V65613/5813canprovidefourcyclesofdataforasingle  
addresspresentedtotheSRAM.Theorderoftheburstsequenceisdefined  
bytheLBOinputpin.TheLBOpinselectsbetweenlinearandinterleaved  
burstsequence.TheADV/LDsignalisusedtoloadanewexternaladdress  
256K x 36, 512K x 18 memory configurations  
Supports high performance system speed - 200MHz  
(3.2ns Clock-to-Data Access)  
ZBTTM Feature - No dead cycles between write and read cycles  
Internally synchronized output buffer enable eliminates the  
need to control OE  
Single R/W (READ/WRITE) control pin  
Positive clock-edge triggered address, data, and control signal  
registers for fully pipelined applications  
4-word burst capability (interleaved or linear)  
Individual byte write (BW1 - BW4) control (May tie active)  
Three chip enables for simple depth expansion  
3.3V power supply (±5%)  
3.3V I/O Supply (VDDQ)  
Power controlled byZZ input.  
Packaged in a JEDEC standard 100-pin plastic thin quad  
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball  
gridarray  
Description  
The IDT71V65613/5813 are 3.3V high-speed 9,437,184-bit (ADV/LD=LOW) orincrementtheinternalburstcounter(ADV/LD=HIGH).  
(9Megabit)synchronousSRAMS.Theyaredesignedtoeliminatedead  
The IDT71V65613/5813 SRAM utilize IDT's latest high-performance  
bus cycles when turning the bus around between reads and writes, or CMOSprocess,andarepackagedinaJEDECStandard14mmx20mm100-  
writesandreads. Thus, theyhavebeengiventhenameZBTTM, orZero pinthinplasticquadflatpack(TQFP)aswellasa119 ballgridarray(BGA)  
Bus Turnaround.  
and 165 fine pitch ball grid array (fBGA).  
PinDescriptionSummary  
A0-A18  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Output  
Input  
I/O  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
N/A  
Chip Enables  
CE1  
, CE  
2
, CE  
2
Output Enable  
OE  
R/W  
Read/Write Signal  
Clock Enable  
CEN  
Individual Byte Write Selects  
Clock  
BW  
1
, BW  
2
, BW  
3
, BW  
4
CLK  
ADV/LD  
LBO  
TMS  
TDI  
Advance burst address / Load new address  
Linear / Interleaved Burst Order  
Test Mode Select  
Test Data input  
Synchronous  
Static  
N/A  
N/A  
TCK  
TDO  
ZZ  
Test Clock  
N/A  
Test Data Output  
Sleep Mode  
N/A  
Asynchronous  
Synchronous  
Static  
I/O  
0
-I/O31, I/OP1-I/OP4  
DD, VDDQ  
SS  
Data Input / Output  
Core Power, I/O Power  
Ground  
V
Supply  
Supply  
V
Static  
5305 tbl 01  
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc.  
NOVEMBER 2000  
1
©2000IntegratedDeviceTechnology,Inc.  
DSC-5305/02  

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