Datasheet > IDT71V65703

IDT71V65703

更新时间： 2024-11-07 22:19:43

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器
页数	文件大小	规格书
26页	497K
描述
256K x 36, 512K x 18 3.3V Synchronous ZBT SRAMs

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IDT71V65703 数据手册

256K x 36, 512K x 18

IDT71V65703

IDT71V65903

3.3VSynchronousZBT™SRAMs

3.3V I/O, Burst Counter

Flow-Through Outputs

cycle,andonthenextclockcycletheassociateddatacycleoccurs,beit

read or write.

TheIDT71V65703/5903containaddress,data-inandcontrolsignal

registers.Theoutputsareflow-through(nooutputdataregister).Output

enable is the only asynchronous signal and can be used to disable the

outputsatanygiventime.

Features

◆

256K x 36, 512K x 18 memory configurations

◆

Supports high performance system speed - 100 MHz

(7.5 ns Clock-to-Data Access)

ZBT^TMFeature - No dead cycles between write and read

◆

cycles

◆

A Clock Enable (CEN) pin allows operation of the IDT71V65703/5903

tobesuspendedaslongasnecessary.Allsynchronousinputsareignoredwhen

CENishighandtheinternaldeviceregisterswillholdtheirpreviousvalues.

There are three chip enable pins (CE¹, CE2, CE2) that allow the

usertodeselectthedevicewhendesired.Ifanyoneofthesethreeisnot

assertedwhenADV/LDislow,nonewmemoryoperationcanbeinitiated.

However,anypendingdatatransfers(readsorwrites)willbecompleted.

Thedatabuswilltri-stateonecycleafterthechipisdeselectedorawrite

isinitiated.

TheIDT71V65703/5903haveanon-chipburstcounter.Intheburst

mode,theIDT71V65703/5903canprovidefourcyclesofdataforasingle

address presented to the SRAM. The order of the burst sequence is

defined by the LBO input pin. The LBO pin selects between linear and

interleaved burst sequence. The ADV/LD signal is used to load a new

externaladdress(ADV/LD=LOW)orincrementtheinternalburstcounter

(ADV/LD = HIGH).

Internally synchronized output buffer enable eliminates the

need to control OE

Single R/W (READ/WRITE) control pin

4-word burst capability (Interleaved or linear)

Individual byte write (BW1 - BW4) control (May tie active)

Three chip enables for simple depth expansion

3.3V power supply (±5%)

3.3V (±5%) I/O Supply (VDDQ)

Power down controlled by ZZ input

◆

Packaged in a JEDEC standard 100-pin plastic thin quad

flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch

ball grid array (fBGA).

Description

The IDT71V65703/5903 are 3.3V high-speed 9,437,184-bit

(9 Megabit) synchronous SRAMs organized as 256K x 36 / 512K x 18.

They are designed to eliminate dead bus cycles when turning the bus

aroundbetweenreads andwrites,orwrites andreads.Thus theyhave

been given the name ZBT^TM, or Zero Bus Turnaround.

AddressandcontrolsignalsareappliedtotheSRAMduringoneclock

TheIDT71V65703/5903SRAMsutilizeIDT’slatesthigh-performance

CMOSprocessandarepackagedinaJEDECStandard14mmx20mm100-

pinplasticthinquadflatpack(TQFP), 119 ballgridarray(BGA)and a 165

fine pitchballgridarray(fBGA).

PinDescriptionSummary

A0-A18

Address Inputs

Input

I/O

Synchronous

Asynchronous

Synchronous

N/A

Chip Enables

CE¹, CE2, CE²

Output Enable

R/W

Read/Write Signal

Clock Enable

CEN

Individual Byte Write Selects

Clock

BW¹, BW², BW³, BW⁴

CLK

ADV/LD

Advance Burst Address/Load New Address

Linear/Interleaved Burst Order

Sleep Mode

Synchronous

Static

LBO

Asynchronous

Synchronous

Static

I/ O0-I/O31, I/OP1-I/OP4

VDD, VDDQ

Data Input/Output

Core Power, I/O Power

Ground

Supply

VSS

Static

5298 tbl 01

ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc.

DECEMBER 2002

DSC-5298/03

12 3 4 5 6 7...26

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与IDT71V65703相关器件

型号	品牌	获取价格	描述	数据表
IDT71V65703_14	IDT	获取价格	3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs
IDT71V6570375BGG	IDT	获取价格	3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs
IDT71V6570375BGG8	IDT	获取价格	3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs
IDT71V6570375BGGI	IDT	获取价格	3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs
IDT71V6570375BGGI8	IDT	获取价格	3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs
IDT71V6570375BQG	IDT	获取价格	3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs
IDT71V6570375BQG8	IDT	获取价格	3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs
IDT71V6570375BQGI	IDT	获取价格	3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs
IDT71V6570375BQGI8	IDT	获取价格	3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs
IDT71V6570375PFG	IDT	获取价格	3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs

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