Datasheet > IDT71V6570375PFGI

IDT71V6570375PFGI

更新时间： 2024-09-20 00:23:19

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器
页数	文件大小	规格书
23页	615K
描述
3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

IDT71V6570375PFGI 数据手册

浏览型号IDT71V6570375PFGI的Datasheet PDF文件第2页

浏览型号IDT71V6570375PFGI的Datasheet PDF文件第3页

浏览型号IDT71V6570375PFGI的Datasheet PDF文件第4页

浏览型号IDT71V6570375PFGI的Datasheet PDF文件第5页

浏览型号IDT71V6570375PFGI的Datasheet PDF文件第6页

浏览型号IDT71V6570375PFGI的Datasheet PDF文件第7页

◆

256K x 36, 512K x 18

IDT71V65703

IDT71V65903

3.3VSynchronousZBT™SRAMs

3.3V I/O, Burst Counter

Flow-Through Outputs

Features

256K x 36, 512K x 18 memory configurations

Address and control signals are applied to the SRAM during one

clock cycle, and on the next clock cycle the associated data cycle

occurs, be it read or write.

The IDT71V65703/5903 contain address, data-in and control

signal registers. The outputs are flow-through (no output data

used to disable the outputs at any given time.

A Clock Enable (CEN) pin allows operation of the IDT71V65703/5903

tobesuspendedaslongasnecessary.Allsynchronousinputsareignoredwhen

CEN is high and the internal device registers will hold their previous values.

There are three chip enable pins (CE1, CE2, CE2) that allow the

user to deselect the device when desired. If any one of these three

is not asserted when ADV/LD is low, no new memory operation can

be initiated. However, any pending data transfers (reads or writes)

will be completed. The data bus will tri-state one cycle after the chip

is deselected or a write is initiated.

Supports high performance system speed - 100 MHz

(7.5 ns Clock-to-Data Access)

ZBT^TMFeature - No dead cycles between write and read

cycles

Internally synchronized output buffer enable eliminates the

need to control OE

Single R/W (READ/WRITE) control pin

4-word burst capability (Interleaved or linear)

Individual byte write (BW1 - BW4) control (May tie active)

Three chip enables for simple depth expansion

3.3V power supply ( 5%)

3.3V ( 5%) I/O Supply (VDDQ)

Power down controlled by ZZ input

Packaged in a JEDEC standard 100-pin plastic thin quad

TheIDT71V65703/5903haveanon-chipburstcounter.Intheburst

mode,theIDT71V65703/5903canprovidefourcyclesofdataforasingle

address presented to the SRAM. The order of the burst sequence is

defined by the LBO input pin. The LBO pin selects between linear and

interleaved burst sequence. The ADV/LD signal is used to load a new

externaladdress(ADV/LD=LOW)orincrementtheinternalburstcounter

(ADV/LD = HIGH).

The IDT71V65703/5903 SRAMs utilize a high-performance CMOS

process and are packaged in a JEDEC Standard 14mm x 20mm 100-

pin plasticthinquadflatpack(TQFP), 119 ballgridarray(BGA) and a 165

fine pitch ball grid array (fBGA).

flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch

ball grid array (fBGA)

Green parts available, see ordering information

Description

The IDT71V65703/5903 are 3.3V high-speed 9,437,184-bit

(9 Megabit) synchronous SRAMs organized as 256K x 36 / 512K x 18.

They are designed to eliminate dead bus cycles when turning the bus

aroundbetweenreadsandwrites, orwritesandreads. Thustheyhave

been given the name ZBT^TM, or Zero Bus Turnaround.

Pin Description Summary

-A18

Address Inputs

Input

I/O

Synchronous

Asynchronous

Synchronous

N/A

Chip Enables

CE , CE

2, CE2

Output Enable

R/W

Read/Write Signal

Clock Enable

CEN

BW , BW

CLK

Individual Byte Write Selects

Clock

2, BW3, BW4

ADV/LD

Advance Burst Address/Load New Address

Linear/Interleaved Burst Order

Sleep Mode

Synchronous

Static

LBO

Asynchronous

Synchronous

Static

I/O

0-I/O31 , I/OP1-I/OP4

Data Input/Output

Core Power, I/O Power

Ground

DD, VDDQ

Supply

Static

5298 tbl 01

ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc.

OCTOBER 2014

DSC-5298/05

12 3 4 5 6 7...23

中文翻译

下载PDF

与IDT71V6570375PFGI相关器件

型号	品牌	获取价格	描述	数据表
IDT71V6570375PFGI8	IDT	获取价格	3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs
IDT71V6570380BGG	IDT	获取价格	3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs
IDT71V6570380BGG8	IDT	获取价格	3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs
IDT71V6570380BGGI	IDT	获取价格	3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs
IDT71V6570380BGGI8	IDT	获取价格	3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs
IDT71V6570380BQG	IDT	获取价格	3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs
IDT71V6570380BQG8	IDT	获取价格	3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs
IDT71V6570380BQGI	IDT	获取价格	3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs
IDT71V6570380BQGI8	IDT	获取价格	3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs
IDT71V6570380PFG	IDT	获取价格	3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs

与IDT71V6570375PFGI相关文章

摩尔斯微电子在美国约书亚树国家公园测试 Wi-Fi HaLow
2024-09-18

25
贸泽上架Tallysman TW5386智能GNSS天线
2024-09-18

23
SL74HC10N：高性能三输入与非门解析
2024-09-03

98
AIC1781A 电池充电控制器深度解析
2024-09-03

89

产品中心

服务支持

精选活动

关于我们

帮助中心

IDT71V6570375PFGI

IDT71V6570375PFGI 数据手册

与IDT71V6570375PFGI相关器件

与IDT71V6570375PFGI相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

IDT71V6570375PFGI

IDT71V6570375PFGI 数据手册

与IDT71V6570375PFGI相关器件

与IDT71V6570375PFGI相关文章

您还可以找

您在本页遇到什么问题？