Datasheet > IDT71V65702S75PFG8

IDT71V65702S75PFG8

更新时间： 2024-11-08 15:42:19

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器内存集成电路
页数	文件大小	规格书
26页	949K
描述
ZBT SRAM, 256KX36, 7.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, GREEN, PLASTIC, TQFP-100

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IDT71V65702S75PFG8 技术参数

生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	LQFP,	针数：	100
Reach Compliance Code：	unknown	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.71
最长访问时间：	7.5 ns	其他特性：	FLOW-THROUGH ARCHITECTURE
JESD-30 代码：	R-PQFP-G100	JESD-609代码：	e0
长度：	20 mm	内存密度：	9437184 bit
内存集成电路类型：	ZBT SRAM	内存宽度：	36
功能数量：	1	端子数量：	100
字数：	262144 words	字数代码：	256000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	256KX36
封装主体材料：	PLASTIC/EPOXY	封装代码：	LQFP
封装形状：	RECTANGULAR	封装形式：	FLATPACK, LOW PROFILE
并行/串行：	PARALLEL	认证状态：	Not Qualified
座面最大高度：	1.6 mm	最大供电电压 (Vsup)：	3.465 V
最小供电电压 (Vsup)：	3.135 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	TIN LEAD
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	QUAD	宽度：	14 mm
Base Number Matches：	1

IDT71V65702S75PFG8 数据手册

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256K x 36, 512K x 18

IDT71V65702

IDT71V65902

3.3VSynchronousZBT™SRAMs

2.5V I/O, Burst Counter

Flow-ThroughOutputs

Features

◆

256K x 36, 512K x 18 memory configurations

Supports high performance system speed - 100 MHz

(7.5 ns Clock-to-Data Access)

occurs,beitreadorwrite.

◆

TheIDT71V65702/5902containaddress,data-inandcontrolsignal

registers.Theoutputsareflow-through(nooutputdataregister).Output

enable is the only asynchronous signal and can be used to disable the

outputsatanygiventime.

ZBT^TMFeature - No dead cycles between write and read

cycles

Internally synchronized output buffer enable eliminates the

need to control OE

Single R/W (READ/WRITE) control pin

4-word burst capability (Interleaved or linear)

Individual byte write (BW¹-BW⁴) control (May tie active)

Three chip enables for simple depth expansion

3.3V power supply (±5%)

2.5V (±5%) I/O Supply (VDDQ)

Power down controlled by ZZ input

Packaged in a JEDEC standard 100-pin plastic thin quad

flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch

ball grid array (fBGA).

AClockEnable(CEN)pinallowsoperationoftheIDT71V65702/5902

tobesuspendedaslongasnecessary.Allsynchronousinputsareignored

whenCENishighandtheinternaldeviceregisterswillholdtheirprevious

values.

There are three chip enable pins (CE1, CE2, CE2) that allow the

usertodeselectthedevicewhendesired.Ifanyoneofthesethreeisnot

assertedwhenADV/LDislow,nonewmemoryoperationcanbeinitiated.

However,anypendingdatatransfers(readsorwrites)willbecompleted.

Thedatabuswilltri-stateonecycleafterthechipisdeselectedorawrite

isinitiated.

TheIDT71V65702/5902haveanon-chipburstcounter.Intheburst

mode,theIDT71V65702/5902canprovidefourcyclesofdataforasingle

address presented to the SRAM. The order of the burst sequence is

defined by the LBO input pin. The LBO pin selects between linear and

interleaved burst sequence. The ADV/LD signal is used to load a new

externaladdress(ADV/LD=LOW)orincrementtheinternalburstcounter

(ADV/LD = HIGH).

TheIDT71V65702/5902SRAMsutilizeIDT’slatesthigh-performance

CMOSprocess,andarepackagedinaJEDECStandard14mmx20mm

100-pin plasticthinquadflatpack(TQFP)aswellasa119 ballgridarray

(BGA) and 165 fine pitch ball grid array (fBGA).

◆

Description

The IDT71V65702/5902 are 3.3V high-speed 9,437,184-bit

(9 Megabit) synchronous SRAMs organized as 256K x 36 / 512K x

18.Theyaredesignedtoeliminatedeadbuscycleswhenturningthe

busaroundbetweenreadsandwrites,orwritesandreads.Thusthey

havebeengiventhenameZBT ,orZeroBusTurnaround.

AddressandcontrolsignalsareappliedtotheSRAMduringone

clock cycle, and on the next clock cycle the associated data cycle

PinDescriptionSummary

A -A

Address Inputs

Input

I/ O

Synchronous

Asynchronous

Synchronous

N/A

Chip Enables

CE , CE , CE

Output Enable

R/W

Read/Write Signal

Clock Enable

CEN

Individual Byte Write Selects

Clock

BW , BW , BW , BW

CLK

ADV/LD

Advance Burst Address/Load New Address

Linear/Interleaved Burst Order

Sleep Mode

Synchronous

Static

LBO

Asynchronous

Synchronous

Static

I/ O0-I/O31, I/OP1-I/OP4

Data Input/Output

Co re Powe r, I/O Powe r

Ground

DD DDQ

, V

Supply

Static

5315 tbl 01

ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc.

OCTOBER 2004

DSC-5315/08

12 3 4 5 6 7...26

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与IDT71V65702S75PFG8相关器件

型号	品牌	获取价格	描述	数据表
IDT71V65702S75PFGI	IDT	获取价格	ZBT SRAM, 256KX36, 7.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
IDT71V65702S80B	IDT	获取价格	ZBT SRAM, 256KX36, 8ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119
IDT71V65702S80BGG	IDT	获取价格	ZBT SRAM, 256KX36, 8ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119
IDT71V65702S80BGGI	IDT	获取价格	ZBT SRAM, 256KX36, 8ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119
IDT71V65702S80BQG	IDT	获取价格	ZBT SRAM, 256KX36, 8ns, CMOS, PBGA165, 13 X 15 MM, FPBGA-165
IDT71V65702S80BQGI	IDT	获取价格	ZBT SRAM, 256KX36, 8ns, CMOS, PBGA165, 13 X 15 MM, FPBGA-165
IDT71V65702S80BQI	IDT	获取价格	ZBT SRAM, 256KX36, 8ns, CMOS, PBGA165, 13 X 15 MM, FPBGA-165
IDT71V65702S80PFG	IDT	获取价格	ZBT SRAM, 256KX36, 8ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, GREEN, PLASTIC, TQFP-10
IDT71V65702S80PFG8	IDT	获取价格	ZBT SRAM, 256KX36, 8ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, GREEN, PLASTIC, TQFP-10
IDT71V65702S80PFGI	IDT	获取价格	ZBT SRAM, 256KX36, 8ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100

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