256K x 36, 512K x 18
3.3V Synchronous ZBT™ SRAMs
Smart ZBT™ Feature
2.5V or 3.3V I/O, Burst Counter
PipelinedOutputs
Preliminary
IDT71V656
IDT71V658
Description
Features
◆
The IDT71V656/58 are 3.3V high-speed 9,437,184-bit
(9 Megabit) synchronous SRAMs. They are designed to eliminate
dead bus cycles when turning the bus around between reads and
writes, or writes and reads. Thus, they have been given the name
256K x 36, 512K x 18 memory configurations
◆
Supports high performance system speed - 200 MHz
(3.2 ns Clock-to-Data Access)
ZBTTM Feature - No dead cycles between write and read
◆
TM
ZBT , or Zero Bus Turnaround.
cycles
◆
Smart ZBTTM Feature - Eases system timing requirements
AddressandcontrolsignalsareappliedtotheSRAMduringoneclock
cycle,andtwocycleslatertheassociateddatacycleoccurs,beitread
or write.
and reduces the likelihood of bus contention
With Smart ZBTTM the output turn-on (tCLZ) is adaptable to
◆
The IDT71V656/58 offer the user an optional Smart functionality
whichsimplifiessystemtimingrequirementswhenturningthebusaround
between writes and reads. Traditionally, SRAMs are designed with
fast turn-on times (tCLZ) in order to meet the requirements of high
speed applications. This fast turn-on may lead to bus contention at
slower speeds, i.e. 133 MHz and slower, since these designs
oftentimes use less aggressive ASICs/controllers with loose turn-off
parameters (tCHZ). Thus at slower speeds, more margin on the
RAM’s tCLZ may be needed to compensate for the slow turn-off of the
ASIC/controller. The IDT71V656/58 have the ability to provide this
extra margin by allowing tCLZ to adapt to the user’s system.
WiththeSmartZBTTM feature,theoutputturn-ontime(tCLZ)adaptsto
the user’s system and is solely a function of cycle time (tCYC). Thus
the user's system and is a function of the cycle time.
◆
Backward compatable with IDT’s existing ZBT offerings.
◆
User selectable Smart ZBTTM or Original ZBTTM mode pin (MS)
◆
Internally synchronized output buffer enable eliminates the
need to control OE
◆
Single R/W (READ/WRITE) control pin
◆
Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications
4-word burst capability (interleaved or linear)
Individual byte write (BW1 - BW4) control (May tie active)
Three chip enables for simple depth expansion
3.3V power supply (±5%)
User selectable 3.3V or 2.5V I/O Supply (VDDQ)
Packaged in a JEDEC standard 100-lead plastic thin quad
◆
◆
◆
◆
◆
TM
◆
with Smart ZBT , tCLZ is independent of process, voltage, and
temperature variations. With this deterministic output turn-on fea-
flatpack (TQFP) and 119-lead ball grid array (BGA).
PinDescriptionSummary
0
18
A -A
Address Inputs
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Chip Enables
1
2
2
CE , CE , CE
Output Enable
OE
R/W
Read/Write Signal
Clock Enable
CEN
Individual Byte Write Selects
Clock
1
2
3
4
BW , BW , BW , BW
CLK
ADV/LD
Advance burst address / Load new address
Linear / Interleaved Burst Order
Data Input / Output
Core Power, I/O Power
Ground
Synchronous
Static
LBO
0
31
P1
P4
I/O -I/O , I/O -I/O
Synchronous
Static
DD DDQ
V , V
Supply
Supply
Input
SS
V
Static
Smart ZBT™ Mode Enable
Static
S
M
5000 tbl 01
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc.
Smart ZBT and Smart Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is also supported by Micron Technology, Inc.
OCTOBER 1999
1
©1999 Integrated Device Technology, Inc.
DSC-5000/04