Datasheet > IDT71V65702

IDT71V65702

更新时间： 2024-09-18 05:39:07

品牌	Logo	应用领域
其他 - ETC		计数器静态存储器
页数	文件大小	规格书
26页	495K
描述
256K x 36, 512K x 18 3.3V Synchronous ZB TM SRAMs 2.5V I/O, Burst Counter Flow-Through Outputs

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

IDT71V65702 数据手册

256K x 36, 512K x 18

IDT71V65702

IDT71V65902

3.3VSynchronousZBT™SRAMs

2.5V I/O, Burst Counter

Flow-ThroughOutputs

Features

◆

256K x 36, 512K x 18 memory configurations

Supports high performance system speed - 100 MHz

(7.5 ns Clock-to-Data Access)

occurs,beitreadorwrite.

◆

TheIDT71V65702/5902containaddress,data-inandcontrolsignal

registers.Theoutputsareflow-through(nooutputdataregister).Output

enable is the only asynchronous signal and can be used to disable the

outputsatanygiventime.

ZBT^TMFeature - No dead cycles between write and read

cycles

Internally synchronized output buffer enable eliminates the

need to control OE

Single R/W (READ/WRITE) control pin

4-word burst capability (Interleaved or linear)

Individual byte write (BW¹-BW⁴) control (May tie active)

Three chip enables for simple depth expansion

3.3V power supply (±5%)

2.5V (±5%) I/O Supply (VDDQ)

Power down controlled by ZZ input

Packaged in a JEDEC standard 100-pin plastic thin quad

flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch

ball grid array (fBGA).

AClockEnable(CEN)pinallowsoperationoftheIDT71V65702/5902

tobesuspendedaslongasnecessary.Allsynchronousinputsareignored

whenCENishighandtheinternaldeviceregisterswillholdtheirprevious

values.

There are three chip enable pins (CE1, CE2, CE2) that allow the

usertodeselectthedevicewhendesired.Ifanyoneofthesethreeisnot

assertedwhenADV/LDislow,nonewmemoryoperationcanbeinitiated.

However,anypendingdatatransfers(readsorwrites)willbecompleted.

Thedatabuswilltri-stateonecycleafterthechipisdeselectedorawrite

isinitiated.

TheIDT71V65702/5902haveanon-chipburstcounter.Intheburst

mode,theIDT71V65702/5902canprovidefourcyclesofdataforasingle

address presented to the SRAM. The order of the burst sequence is

defined by the LBO input pin. The LBO pin selects between linear and

interleaved burst sequence. The ADV/LD signal is used to load a new

externaladdress(ADV/LD=LOW)orincrementtheinternalburstcounter

(ADV/LD = HIGH).

TheIDT71V65702/5902SRAMsutilizeIDT’slatesthigh-performance

CMOSprocess,andarepackagedinaJEDECStandard14mmx20mm

100-pin plasticthinquadflatpack(TQFP)aswellasa119 ballgridarray

(BGA) and 165 fine pitch ball grid array (fBGA).

◆

Description

The IDT71V65702/5902 are 3.3V high-speed 9,437,184-bit

(9 Megabit) synchronous SRAMs organized as 256K x 36 / 512K x

18.Theyaredesignedtoeliminatedeadbuscycleswhenturningthe

busaroundbetweenreadsandwrites,orwritesandreads.Thusthey

havebeengiventhenameZBT ,orZeroBusTurnaround.

AddressandcontrolsignalsareappliedtotheSRAMduringone

clock cycle, and on the next clock cycle the associated data cycle

PinDescriptionSummary

A -A

Address Inputs

Input

I/ O

Synchronous

Asynchronous

Synchronous

N/A

Chip Enables

CE , CE , CE

Output Enable

R/W

Read/Write Signal

Clock Enable

CEN

Individual Byte Write Selects

Clock

BW , BW , BW , BW

CLK

ADV/LD

Advance Burst Address/Load New Address

Linear/Interleaved Burst Order

Sleep Mode

Synchronous

Static

LBO

Asynchronous

Synchronous

Static

I/ O0-I/O31, I/OP1-I/OP4

Data Input/Output

Co re Powe r, I/O Powe r

Ground

DD DDQ

, V

Supply

Static

5315 tbl 01

ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc.

OCTOBER 2004

DSC-5315/08

12 3 4 5 6 7...26

中文翻译

下载PDF

与IDT71V65702相关器件

型号	品牌	获取价格	描述	数据表
IDT71V65702S75B	IDT	获取价格	ZBT SRAM, 256KX36, 7.5ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119
IDT71V65702S75BGGI	IDT	获取价格	ZBT SRAM, 256KX36, 7.5ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119
IDT71V65702S75BQ	IDT	获取价格	ZBT SRAM, 256KX36, 7.5ns, CMOS, PBGA165, 13 X 15 MM, FPBGA-165
IDT71V65702S75BQG	IDT	获取价格	ZBT SRAM, 256KX36, 7.5ns, CMOS, PBGA165, 13 X 15 MM, FPBGA-165
IDT71V65702S75BQGI	IDT	获取价格	ZBT SRAM, 256KX36, 7.5ns, CMOS, PBGA165, 13 X 15 MM, FPBGA-165
IDT71V65702S75PFG	IDT	获取价格	ZBT SRAM, 256KX36, 7.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, GREEN, PLASTIC, TQFP-
IDT71V65702S75PFG8	IDT	获取价格	ZBT SRAM, 256KX36, 7.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, GREEN, PLASTIC, TQFP-
IDT71V65702S75PFGI	IDT	获取价格	ZBT SRAM, 256KX36, 7.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
IDT71V65702S80B	IDT	获取价格	ZBT SRAM, 256KX36, 8ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119
IDT71V65702S80BGG	IDT	获取价格	ZBT SRAM, 256KX36, 8ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119

与IDT71V65702相关文章

摩尔斯微电子在美国约书亚树国家公园测试 Wi-Fi HaLow
2024-09-18

23
贸泽上架Tallysman TW5386智能GNSS天线
2024-09-18

21
SL74HC10N：高性能三输入与非门解析
2024-09-03

96
AIC1781A 电池充电控制器深度解析
2024-09-03

87

产品中心

服务支持

精选活动

关于我们

帮助中心

IDT71V65702

IDT71V65702 数据手册

与IDT71V65702相关器件

与IDT71V65702相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

IDT71V65702

IDT71V65702 数据手册

与IDT71V65702相关器件

与IDT71V65702相关文章

您还可以找

您在本页遇到什么问题？