Datasheet > 存储 > SRAM> IDT71T75602S100PFI

IDT71T75602S100PFI

更新时间： 2024-11-29 22:37:03

品牌	Logo	应用领域
艾迪悌 - IDT		计数器静态存储器
页数	文件大小	规格书
25页	639K
描述
512K x 36, 1M x 18 2.5V Synchronous ZBT⑩ SRAMs 2.5V I/O, Burst Counter Pipelined Outputs

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512K x 36, 1M x 18

IDT71T75602

IDT71T75802

2.5V Synchronous ZBT™ SRAMs

2.5V I/O, Burst Counter

PipelinedOutputs

Features

◆

Description

512K x 36, 1M x 18 memory configurations

◆

The IDT71T75602/802 are 2.5V high-speed 18,874,368-bit

(18 Megabit)synchronousSRAMs.Theyaredesignedtoeliminatedead

bus cycles when turning the bus around between reads and writes, or

Supports high performance system speed - 225 MHz

(3.0 ns Clock-to-Data Access)

ZBT^TMFeature - No dead cycles between write and read

◆

writes andreads.Thus,theyhavebeengiventhenameZBT ,orZero

Bus Turnaround.

cycles

◆

Internally synchronized output buffer enable eliminates the

Address and control signals are applied to the SRAM during one

clockcycle,andtwocycles latertheassociateddatacycleoccurs,beit

read or write.

need to control OE

◆

Single R/W (READ/WRITE) control pin

◆

Positive clock-edge triggered address, data, and control

TheIDT71T75602/802containdataI/O,addressandcontrolsignal

registers.Outputenableistheonlyasynchronoussignalandcanbeused

todisabletheoutputsatanygiventime.

AClockEnable CEN pinallows operationofthe IDT71T75602/802

tobesuspendedaslongasnecessary.Allsynchronousinputsareignored

when(CEN)ishighandtheinternaldeviceregisterswillholdtheirprevious

values.

There are three chip enable pins (CE¹, CE2, CE2) that allow the

usertodeselectthedevicewhendesired.Ifanyoneofthesethreeisnot

assertedwhenADV/LDislow,nonewmemoryoperationcanbeinitiated.

signal registers for fully pipelined applications

4-word burst capability (interleaved or linear)

Individual byte write (BW1 - BW4) control (May tie active)

Three chip enables for simple depth expansion

2.5V power supply (±5%)

2.5V I/O Supply (VDDQ)

Power down controlled by ZZ input

Boundary Scan JTAG Interface (IEEE 1149.1 Compliant)

◆

Packaged in a JEDEC standard 100-pin plastic thin quad

flatpack (TQFP), 119 ball grid array (BGA)

PinDescriptionSummary

A⁰-A¹⁹

Address Inputs

Input

Output

Input

I/O

Synchronous

Asynchronous

Synchronous

N/A

Chip Enables

CE¹, CE², CE2

Output Enable

Read/Write Signal

Clock Enable

CEN

Individual Byte Write Selects

Clock

BW¹, BW², BW³, BW4

CLK

ADV/LD

Advance burst address / Load new address

Linear / Interleaved Burst Order

Test Mode Select

Test Data Input

Synchronous

Static

LBO

TMS

N/A

TDI

N/A

TCK

Test Clock

N/A

TDO

Test Data Input

N/A

JTAG Reset (Optional)

Sleep Mode

Asynchronous

Synchronous

Static

TRST

I/O⁰-I/O³¹, I/O^P1-I/O^P4

V^DD, V^DDQ

Data Input / Output

Core Power, I/O Power

Ground

Supply

V^SS

Static

5313 tbl 01

APRIL 2004

DSC-5313/08

12 3 4 5 6 7...25

中文翻译

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IDT71T75602S100PFI 替代型号

型号	品牌	替代类型	描述	数据表
IDT71T75602S100PF	IDT	完全替代	512K x 36, 1M x 18 2.5V Synchronous ZBT⑩ SRAM
IDT71T75602S100PF8	IDT	功能相似	ZBT SRAM, 512KX36, 5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MO-136DJ, TQFP

与IDT71T75602S100PFI相关器件

型号	品牌	获取价格	描述	数据表
IDT71T75602S100PFI8	IDT	获取价格	ZBT SRAM, 512KX36, 5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MO-136DJ, TQFP
IDT71T75602S133BG	IDT	获取价格	512K x 36, 1M x 18 2.5V Synchronous ZBT⑩ SRAM
IDT71T75602S133BGI	IDT	获取价格	512K x 36, 1M x 18 2.5V Synchronous ZBT⑩ SRAM
IDT71T75602S133PF	IDT	获取价格	512K x 36, 1M x 18 2.5V Synchronous ZBT⑩ SRAM
IDT71T75602S133PF8	IDT	获取价格	ZBT SRAM, 512KX36, 4.2ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MO-136DJ, TQ
IDT71T75602S133PFI	IDT	获取价格	512K x 36, 1M x 18 2.5V Synchronous ZBT⑩ SRAM
IDT71T75602S133PFI8	IDT	获取价格	ZBT SRAM, 512KX36, 4.2ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MO-136DJ, TQ
IDT71T75602S150BG	IDT	获取价格	512K x 36, 1M x 18 2.5V Synchronous ZBT⑩ SRAM
IDT71T75602S150BG8	IDT	获取价格	ZBT SRAM, 512KX36, 3.8ns, CMOS, PBGA119, 14 X 22 MM, MS-028-AA, BGA-119
IDT71T75602S150BGG	IDT	获取价格	暂无描述

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