Datasheet > IDT71T75602S166BQ

IDT71T75602S166BQ

更新时间： 2024-12-01 03:06:23

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器
页数	文件大小	规格书
25页	462K
描述
ZBT SRAM, 512KX36, 3.5ns, CMOS, PBGA165, 13 X 15 MM, FBGA-165

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Information

IDT71T75602

IDT71T75802

512K x 36, 1M x 18

2.5V Synchronous ZBT™ SRAMs

2.5V I/O, Burst Counter

PipelinedOutputs

Features

◆

Description

512K x 36, 1M x 18 memory configurations

◆

The IDT71T75602/802 are 2.5V high-speed 18,874,368-bit

(18 Megabit)synchronousSRAMs.Theyaredesignedtoeliminatedead

bus cycles when turning the bus around between reads and writes, or

Supports high performance system speed - 166 MHz

(3.5 ns Clock-to-Data Access)

ZBT^TMFeature - No dead cycles between write and read

◆

writes andreads.Thus,theyhavebeengiventhenameZBT ,orZero

Bus Turnaround.

cycles

◆

Internally synchronized output buffer enable eliminates the

Address and control signals are applied to the SRAM during one

clockcycle,andtwocycles latertheassociateddatacycleoccurs,beit

read or write.

need to control OE

Single R/W (READ/WRITE) control pin

Positive clock-edge triggered address, data, and control

◆

TheIDT71T75602/802containdataI/O,addressandcontrolsignal

registers.Outputenableistheonlyasynchronoussignalandcanbeused

todisabletheoutputsatanygiventime.

AClockEnable CEN pinallows operationofthe IDT71T75602/802

tobesuspendedaslongasnecessary.Allsynchronousinputsareignored

when(CEN)ishighandtheinternaldeviceregisterswillholdtheirprevious

values.

There are three chip enable pins (CE¹, CE2, CE2) that allow the

usertodeselectthedevicewhendesired.Ifanyoneofthesethreeisnot

assertedwhenADV/LDislow,nonewmemoryoperationcanbeinitiated.

signal registers for fully pipelined applications

4-word burst capability (interleaved or linear)

Individual byte write (BW1 - BW4) control (May tie active)

Three chip enables for simple depth expansion

2.5V power supply (±5%)

2.5V I/O Supply (VDDQ)

Power down controlled by ZZ input

Packaged in a JEDEC standard 100-pin plastic thin quad

◆

flatpack (TQFP), 119 ball grid array (BGA) and a 165 fine

pitch ball grid array (fBGA).

PinDescriptionSummary

A⁰-A¹⁹

Address Inputs

Input

Output

Input

I/O

Synchronous

Asynchronous

Synchronous

N/A

Chip Enables

CE , CE , CE

Output Enable

R/W

CEN

Read/Write Signal

Clock Enable

Individual Byte Write Selects

Clock

BW , BW , BW , BW

CLK

ADV/LD

LBO

TMS

TDI

Advance burst address / Load new address

Linear / Interleaved Burst Order

Test Mode Select

Test Data Input

Synchronous

Static

N/A

TCK

TDO

Test Clock

N/A

Test Data Input

N/A

Sleep Mode

Synchronous

Static

I/O -I/O , I/O -I/O

Data Input / Output

Core Power, I/O Power

Ground

DD DDQ

V , V

Supply

Static

5313 tbl 01

ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc.

MAY 2000

DSC-5313/00

12 3 4 5 6 7...25

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与IDT71T75602S166BQ相关器件

型号	品牌	获取价格	描述	数据表
IDT71T75602S166PF	IDT	获取价格	512K x 36, 1M x 18 2.5V Synchronous ZBT⑩ SRAM
IDT71T75602S166PF8	IDT	获取价格	ZBT SRAM, 512KX36, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MO-136DJ, TQ
IDT71T75602S166PFG8	IDT	获取价格	ZBT SRAM, 512KX36, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, GREEN, PLASTIC, MO-13
IDT71T75602S166PFGI	IDT	获取价格	ZBT SRAM, 512KX36, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MO-136DJ, TQ
IDT71T75602S166PFI	IDT	获取价格	512K x 36, 1M x 18 2.5V Synchronous ZBT⑩ SRAM
IDT71T75602S166PFI8	IDT	获取价格	ZBT SRAM, 512KX36, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MO-136DJ, TQ
IDT71T75602S200BG	IDT	获取价格	512K x 36, 1M x 18 2.5V Synchronous ZBT⑩ SRAM
IDT71T75602S200BGG	IDT	获取价格	ZBT SRAM, 512KX36, 3.2ns, CMOS, PBGA119, 14 X 22 MM, MS-028-AA, BGA-119
IDT71T75602S200BGG8	IDT	获取价格	ZBT SRAM, 512KX36, 3.2ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, MS-028AA, BGA-119
IDT71T75602S200BGGI	IDT	获取价格	ZBT SRAM, 512KX36, 3.2ns, CMOS, PBGA119, 14 X 22 MM, MS-028-AA, BGA-119

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