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IDT71T75602S200BGGI8 PDF预览

IDT71T75602S200BGGI8

更新时间: 2024-12-01 19:05:03
品牌 Logo 应用领域
艾迪悌 - IDT 时钟静态存储器内存集成电路
页数 文件大小 规格书
26页 287K
描述
ZBT SRAM, 512KX36, 3.2ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, MS-028AA, BGA-119

IDT71T75602S200BGGI8 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:BGA包装说明:14 X 22 MM, PLASTIC, MS-028AA, BGA-119
针数:119Reach Compliance Code:unknown
ECCN代码:3A991.B.2.AHTS代码:8542.32.00.41
风险等级:5.14最长访问时间:3.2 ns
其他特性:PIPELINED ARCHITECTURE最大时钟频率 (fCLK):200 MHz
I/O 类型:COMMONJESD-30 代码:R-PBGA-B119
JESD-609代码:e1长度:22 mm
内存密度:18874368 bit内存集成电路类型:ZBT SRAM
内存宽度:36湿度敏感等级:3
功能数量:1端子数量:119
字数:524288 words字数代码:512000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:512KX36
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装等效代码:BGA119,7X17,50
封装形状:RECTANGULAR封装形式:GRID ARRAY
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:2.5 V认证状态:Not Qualified
座面最大高度:2.36 mm最小待机电流:2.38 V
子类别:SRAMs最大供电电压 (Vsup):2.625 V
最小供电电压 (Vsup):2.375 V标称供电电压 (Vsup):2.5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Silver/Copper (Sn/Ag/Cu)
端子形式:BALL端子节距:1.27 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:14 mmBase Number Matches:1

IDT71T75602S200BGGI8 数据手册

 浏览型号IDT71T75602S200BGGI8的Datasheet PDF文件第2页浏览型号IDT71T75602S200BGGI8的Datasheet PDF文件第3页浏览型号IDT71T75602S200BGGI8的Datasheet PDF文件第4页浏览型号IDT71T75602S200BGGI8的Datasheet PDF文件第5页浏览型号IDT71T75602S200BGGI8的Datasheet PDF文件第6页浏览型号IDT71T75602S200BGGI8的Datasheet PDF文件第7页 
512K x 36, 1M x 18  
IDT71T75602  
IDT71T75802  
2.5V Synchronous ZBT™ SRAMs  
2.5V I/O, Burst Counter  
Pipelined Outputs  
Features  
512K x 36, 1M x 18 memory configurations  
4-word burst capability (interleaved or linear)  
Supports high performance system speed - 200 MHz  
Individual byte write (BW1 - BW4) control (May tie active)  
Three chip enables for simple depth expansion  
2.5V power supply (±5%)  
2.5V I/O Supply (VDDQ)  
Power down controlled by ZZ input  
Boundary Scan JTAG Interface (IEEE 1149.1 Compliant)  
Packaged in a JEDEC standard 100-pin plastic thin quad  
flatpack (TQFP), 119 ball grid array (BGA)  
Green parts available, see Ordering Information  
(3.2 ns Clock-to-Data Access)  
ZBTTM Feature - No dead cycles between write and read  
cycles  
Internally synchronized output buffer enable eliminates the  
need to control OE  
Single R/W (READ/WRITE) control pin  
Positive clock-edge triggered address, data, and control  
signal registers for fully pipelinedapplications  
Functional Block Diagram - 512K x 36  
LBO  
512Kx36 BIT  
MEMORY ARRAY  
Address A [0:18]  
D
D
Q
Q
Address  
CE1, CE2, CE2  
R/W  
Control  
CEN  
ADV/LD  
BW  
DI DO  
x
D
Q
Control Logic  
Clk  
Mux  
Sel  
D
Clock  
Output Register  
Q
Gate  
OE  
TMS  
TDI  
TCK  
Data I/O [0:31],  
I/O P[1:4]  
JTAG  
TDO  
TRST  
5313 drw 01  
(optional)  
OCTOBER 2017  
1
©2017 Integrated Device Technology, Inc.  
DSC-5313/11  

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