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IDT71T7570280BG PDF预览

IDT71T7570280BG

更新时间: 2024-12-02 00:42:11
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器
页数 文件大小 规格书
26页 395K
描述
Synchronous ZBT SRAMs

IDT71T7570280BG 数据手册

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512K x 36, 1M x 18  
2.5V Synchronous ZBT™ SRAMs  
2.5V I/O, Burst Counter  
Flow-Through Outputs  
IDT71T75702  
IDT71T75902  
Features  
The IDT71T75702/902 contain address, data-in and control signal  
registers.Theoutputsareflow-through(nooutputdataregister).Output  
enable is the only asynchronous signal and can be used to disable the  
outputsatanygiventime.  
AClockEnable(CEN)pinallowsoperationoftheIDT71T75702/902  
to be suspended as long as necessary. All synchronous inputs are  
ignoredwhenCENishighandtheinternaldeviceregisterswillholdtheir  
previous values.  
There are three chip enable pins (CE1, CE2, CE2) that allow the  
usertodeselectthedevicewhendesired.Ifanyoneofthesethreeisnot  
assertedwhenADV/LDislow,nonewmemoryoperationcanbeinitiated.  
However,anypendingdatatransfers(readsorwrites)willbecompleted.  
Thedatabuswilltri-stateonecycleafterthechipisdeselectedorawrite  
isinitiated.  
The IDT71T75702/902 have an on-chip burst counter. In the burst  
mode,theIDT71T75702/902canprovidefourcyclesofdataforasingle  
address presented to the SRAM. The order of the burst sequence is  
defined by the LBO input pin. The LBO pin selects between linear and  
interleaved burst sequence. The ADV/LD signal is used to load a new  
externaladdress(ADV/LD=LOW)orincrementtheinternalburstcounter  
(ADV/LD = HIGH).  
512K x 36, 1M x 18 memory configurations  
Supports high performance system speed - 100 MHz  
(7.5 ns Clock-to-Data Access)  
ZBT Feature - No dead cycles between write and read cycles  
Internally synchronized output buffer enable eliminates the  
need to control OE  
Single R/W (READ/WRITE) control pin  
4-word burst capability (Interleaved or linear)  
Individual byte write (BW1 - BW4) control (May tie active)  
Three chip enables for simple depth expansion  
2.5V power supply (±5%)  
2.5V (±5%) I/O Supply (VDDQ)  
Power down controlled by ZZ input  
TM  
Boundary Scan JTAG Interface (IEEE 1149.1 Compliant)  
Packaged in a JEDEC standard 100-pin plastic thin quad  
flatpack (TQFP), 119 ball grid array (BGA)  
Description  
The IDT71T75702/902 are 2.5V high-speed 18,874,368-bit  
(18 Megabit) synchronous SRAMs organized as 512K x 36 /1M x 18.  
They are designed to eliminate dead bus cycles when turning the bus  
aroundbetweenreadsandwrites,orwritesandreads.Thustheyhave  
The IDT71T75702/902 SRAMs utilize IDT’s high-performance  
CMOSprocess,andarepackagedinaJEDECStandard14mmx20mm  
100-pinplasticthinquadflatpack(TQFP)aswellasa119 ballgridarray  
(BGA).  
TM  
been given the name ZBT , or Zero Bus Turnaround.  
AddressandcontrolsignalsareappliedtotheSRAMduringoneclock  
cycle,andonthenextclockcycletheassociateddatacycleoccurs,be  
it read or write.  
PinDescriptionSummary  
A0-A19  
Ad d re ss Inp uts  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Output  
Input  
Input  
I/ O  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
N/A  
Chip Enables  
CE1, CE2, CE2  
OE  
Output Enable  
W
R/  
CEN  
BW1 BW2 BW3 BW4  
Read/Write Signal  
Clock Enable  
Individual Byte Write Selects  
Clock  
,
,
,
CLK  
ADV/LD  
Advance Burst Address/Load New Address  
Linear/Interleaved Burst Order  
Tes t Mo de S el e ct  
Test Data Input  
Synchronous  
Static  
LBO  
TMS  
TDI  
N/A  
N/A  
TCK  
TDO  
Te s t C loc k  
N/A  
Te s t D ata Outp ut  
JTAG Reset (Optional)  
Sleep Mode  
N/A  
Asynchronous  
Synchronous  
Synchronous  
Static  
TRST  
ZZ  
I/ O0-I/O31, I/OP1-I/OP4  
VDD, VDDQ  
Data Input/Output  
Co re Po wer, I/O Power  
Ground  
Supply  
Supply  
VSS  
Static  
5319 tbl 01  
FEBRUARY 2009  
1
©2004IntegratedDeviceTechnology,Inc.  
DSC-5319/08  

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