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IDT71T75702S80PFG8 PDF预览

IDT71T75702S80PFG8

更新时间: 2024-12-01 19:20:47
品牌 Logo 应用领域
艾迪悌 - IDT 时钟静态存储器内存集成电路
页数 文件大小 规格书
23页 217K
描述
ZBT SRAM, 512KX36, 8ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, GREEN, PLASTIC, TQFP-100

IDT71T75702S80PFG8 技术参数

是否Rohs认证:符合生命周期:Obsolete
零件包装代码:QFP包装说明:14 X 20 MM, 1.40 MM HEIGHT, GREEN, PLASTIC, TQFP-100
针数:100Reach Compliance Code:compliant
ECCN代码:3A991.B.2.AHTS代码:8542.32.00.41
风险等级:5.84Is Samacsys:N
最长访问时间:8 ns其他特性:FLOW-THROUGH ARCHITECTURE
最大时钟频率 (fCLK):95 MHzI/O 类型:COMMON
JESD-30 代码:R-PQFP-G100JESD-609代码:e3
长度:20 mm内存密度:18874368 bit
内存集成电路类型:ZBT SRAM内存宽度:36
功能数量:1端子数量:100
字数:524288 words字数代码:512000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:512KX36
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装等效代码:QFP100,.63X.87
封装形状:RECTANGULAR封装形式:FLATPACK, LOW PROFILE
并行/串行:PARALLEL电源:2.5 V
认证状态:Not Qualified座面最大高度:1.6 mm
最大待机电流:0.04 A最小待机电流:2.38 V
子类别:SRAMs最大压摆率:0.25 mA
最大供电电压 (Vsup):2.625 V最小供电电压 (Vsup):2.375 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:MATTE TIN端子形式:GULL WING
端子节距:0.65 mm端子位置:QUAD
宽度:14 mmBase Number Matches:1

IDT71T75702S80PFG8 数据手册

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1M x 18  
2.5V Synchronous ZBT™ SRAM  
2.5V I/O, Burst Counter  
Flow-Through Outputs  
IDT71T75902  
Features  
Three chip enables for simple depth expansion  
2.5V power supply (±5%)  
2.5V (±5%) I/O Supply (VDDQ)  
Power down controlled by ZZ input  
Boundary Scan JTAG Interface (IEEE 1149.1 Compliant)  
Packaged in a JEDEC standard 100-pin plastic thin quad  
flatpack (TQFP), 119 ball grid array (BGA)  
1M x 18 memory configuration  
Supports high performance system speed - 100 MHz  
(7.5 ns Clock-to-Data Access)  
ZBTTM Feature - No dead cycles between write and read cycles  
Internally synchronized output buffer enable eliminates the  
need to control OE  
Single R/W (READ/WRITE) control pin  
4-word burst capability (Interleaved or linear)  
Individual byte write (BW1 - BW2 control (May tie active)  
Green parts available, see Ordering Information  
Functional Block Diagram — 1M x 18  
LBO  
1M x 18 BIT  
MEMORY ARRAY  
Address  
Address A [0:19]  
D
D
Q
Q
CE1, CE2 CE2  
R/W  
CEN  
Control  
ADV/LD  
BWx  
DI  
DO  
D
Q
Control Logic  
Clk  
Mux  
Sel  
Clock  
OE  
Gate  
TMS  
Data I/O [0:15], I/O P[1:2]  
TDI  
TCK  
5319 drw 01a  
TDO  
JTAG  
TRST  
(optional)  
SEPTEMBER 2017  
1
©2017 Integrated Device Technology, Inc.  
DSC-5319/10  

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