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IDT71T75602S225BG8 PDF预览

IDT71T75602S225BG8

更新时间: 2024-12-01 19:37:35
品牌 Logo 应用领域
艾迪悌 - IDT 时钟静态存储器内存集成电路
页数 文件大小 规格书
23页 473K
描述
ZBT SRAM, 512KX36, 3ns, CMOS, PBGA119, 14 X 22 MM, MS-028-AA, BGA-119

IDT71T75602S225BG8 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:BGA
包装说明:14 X 22 MM, MS-028-AA, BGA-119针数:119
Reach Compliance Code:not_compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.74
最长访问时间:3 ns其他特性:PIPELINED ARCHITECTURE
最大时钟频率 (fCLK):225 MHzI/O 类型:COMMON
JESD-30 代码:R-PBGA-B119JESD-609代码:e0
长度:22 mm内存密度:18874368 bit
内存集成电路类型:ZBT SRAM内存宽度:36
湿度敏感等级:3功能数量:1
端子数量:119字数:524288 words
字数代码:512000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:512KX36输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装等效代码:BGA119,7X17,50封装形状:RECTANGULAR
封装形式:GRID ARRAY并行/串行:PARALLEL
峰值回流温度(摄氏度):225电源:2.5 V
认证状态:Not Qualified座面最大高度:2.36 mm
最大待机电流:0.04 A最小待机电流:2.38 V
子类别:SRAMs最大压摆率:0.315 mA
最大供电电压 (Vsup):2.625 V最小供电电压 (Vsup):2.375 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn63Pb37)端子形式:BALL
端子节距:1.27 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:20宽度:14 mm
Base Number Matches:1

IDT71T75602S225BG8 数据手册

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Advance  
Information  
IDT71T75602  
IDT71T75802  
512K x 36, 1M x 18  
2.5V Synchronous ZBT™ SRAMs  
2.5V I/O, Burst Counter  
PipelinedOutputs  
Description  
Features  
The IDT71T75602/802 are 2.5V high-speed 18,874,368-bit  
(18 Megabit)synchronousSRAMs.Theyaredesignedtoeliminatedead  
bus cycles when turning the bus around between reads and writes, or  
512K x 36, 1M x 18 memory configurations  
Supports high performance system speed - 166 MHz  
(3.5 ns Clock-to-Data Access)  
ZBTTM Feature - No dead cycles between write and read  
TM  
writes andreads.Thus,theyhavebeengiventhenameZBT ,orZero  
Bus Turnaround.  
cycles  
Address and control signals are applied to the SRAM during one  
clockcycle,andtwocycles latertheassociateddatacycleoccurs,beit  
read or write.  
TheIDT71T75602/802containdataI/O,addressandcontrolsignal  
registers.Outputenableistheonlyasynchronoussignalandcanbeused  
todisabletheoutputsatanygiventime.  
AClockEnable CEN pinallows operationofthe IDT71T75602/802  
tobesuspendedaslongasnecessary.Allsynchronousinputsareignored  
when(CEN)ishighandtheinternaldeviceregisterswillholdtheirprevious  
values.  
There are three chip enable pins (CE1, CE2, CE2) that allow the  
usertodeselectthedevicewhendesired.Ifanyoneofthesethreeisnot  
assertedwhenADV/LDislow,nonewmemoryoperationcanbeinitiated.  
However,anypendingdatatransfers(readsorwrites)willbecompleted.  
Internally synchronized output buffer enable eliminates the  
need to control OE  
Single R/W (READ/WRITE) control pin  
Positive clock-edge triggered address, data, and control  
signal registers for fully pipelined applications  
4-word burst capability (interleaved or linear)  
Individual byte write (BW1 - BW4) control (May tie active)  
Three chip enables for simple depth expansion  
2.5V power supply (±5%)  
2.5V I/O Supply (VDDQ)  
Power down controlled by ZZ input  
Packaged in a JEDEC standard 100-pin plastic thin quad  
flatpack (TQFP), 119 ball grid array (BGA)  
PinDescriptionSummary  
A0-A19  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Output  
Input  
I/O  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
N/A  
Chip Enables  
1
2
2
CE , CE , CE  
Output Enable  
OE  
R/W  
CEN  
Read/Write Signal  
Clock Enable  
Individual Byte Write Selects  
Clock  
1
2
3
4
BW , BW , BW , BW  
CLK  
ADV/LD  
LBO  
TMS  
TDI  
Advance burst address / Load new address  
Linear / Interleaved Burst Order  
Test Mode Select  
Test Data Input  
Synchronous  
Static  
N/A  
N/A  
TCK  
TDO  
ZZ  
Test Clock  
N/A  
Test Data Input  
N/A  
Sleep Mode  
Synchronous  
Synchronous  
Static  
0
31  
P1  
P4  
I/O -I/O , I/O -I/O  
Data Input / Output  
Core Power, I/O Power  
Ground  
DD DDQ  
V , V  
Supply  
Supply  
SS  
V
Static  
5313 tbl 01  
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc.  
DECEMBER 2001  
1
©2000IntegratedDeviceTechnology,Inc.  
DSC-5313/04  

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