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IDT71T75602S100PF PDF预览

IDT71T75602S100PF

更新时间: 2024-11-29 22:37:03
品牌 Logo 应用领域
艾迪悌 - IDT 计数器静态存储器
页数 文件大小 规格书
25页 639K
描述
512K x 36, 1M x 18 2.5V Synchronous ZBT⑩ SRAMs 2.5V I/O, Burst Counter Pipelined Outputs

IDT71T75602S100PF 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MO-136DJ, TQFP-100
针数:100Reach Compliance Code:not_compliant
ECCN代码:3A991.B.2.AHTS代码:8542.32.00.41
风险等级:5.81最长访问时间:5 ns
其他特性:PIPELINED ARCHITECTURE最大时钟频率 (fCLK):100 MHz
I/O 类型:COMMONJESD-30 代码:R-PQFP-G100
JESD-609代码:e0长度:20 mm
内存密度:18874368 bit内存集成电路类型:ZBT SRAM
内存宽度:36湿度敏感等级:3
功能数量:1端子数量:100
字数:524288 words字数代码:512000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:512KX36
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装等效代码:QFP100,.63X.87
封装形状:RECTANGULAR封装形式:FLATPACK, LOW PROFILE
并行/串行:PARALLEL峰值回流温度(摄氏度):240
电源:2.5 V认证状态:Not Qualified
座面最大高度:1.6 mm最大待机电流:0.04 A
最小待机电流:2.38 V子类别:SRAMs
最大压摆率:0.175 mA最大供电电压 (Vsup):2.625 V
最小供电电压 (Vsup):2.375 V标称供电电压 (Vsup):2.5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:0.65 mm
端子位置:QUAD处于峰值回流温度下的最长时间:20
宽度:14 mm

IDT71T75602S100PF 数据手册

 浏览型号IDT71T75602S100PF的Datasheet PDF文件第2页浏览型号IDT71T75602S100PF的Datasheet PDF文件第3页浏览型号IDT71T75602S100PF的Datasheet PDF文件第4页浏览型号IDT71T75602S100PF的Datasheet PDF文件第5页浏览型号IDT71T75602S100PF的Datasheet PDF文件第6页浏览型号IDT71T75602S100PF的Datasheet PDF文件第7页 
512K x 36, 1M x 18  
IDT71T75602  
IDT71T75802  
2.5V Synchronous ZBT™ SRAMs  
2.5V I/O, Burst Counter  
PipelinedOutputs  
Features  
Description  
512K x 36, 1M x 18 memory configurations  
The IDT71T75602/802 are 2.5V high-speed 18,874,368-bit  
(18 Megabit)synchronousSRAMs.Theyaredesignedtoeliminatedead  
bus cycles when turning the bus around between reads and writes, or  
Supports high performance system speed - 225 MHz  
(3.0 ns Clock-to-Data Access)  
ZBTTM Feature - No dead cycles between write and read  
TM  
writes andreads.Thus,theyhavebeengiventhenameZBT ,orZero  
Bus Turnaround.  
cycles  
Internally synchronized output buffer enable eliminates the  
Address and control signals are applied to the SRAM during one  
clockcycle,andtwocycles latertheassociateddatacycleoccurs,beit  
read or write.  
need to control OE  
Single R/W (READ/WRITE) control pin  
Positive clock-edge triggered address, data, and control  
TheIDT71T75602/802containdataI/O,addressandcontrolsignal  
registers.Outputenableistheonlyasynchronoussignalandcanbeused  
todisabletheoutputsatanygiventime.  
AClockEnable CEN pinallows operationofthe IDT71T75602/802  
tobesuspendedaslongasnecessary.Allsynchronousinputsareignored  
when(CEN)ishighandtheinternaldeviceregisterswillholdtheirprevious  
values.  
There are three chip enable pins (CE1, CE2, CE2) that allow the  
usertodeselectthedevicewhendesired.Ifanyoneofthesethreeisnot  
assertedwhenADV/LDislow,nonewmemoryoperationcanbeinitiated.  
signal registers for fully pipelined applications  
4-word burst capability (interleaved or linear)  
Individual byte write (BW1 - BW4) control (May tie active)  
Three chip enables for simple depth expansion  
2.5V power supply (±5%)  
2.5V I/O Supply (VDDQ)  
Power down controlled by ZZ input  
Boundary Scan JTAG Interface (IEEE 1149.1 Compliant)  
Packaged in a JEDEC standard 100-pin plastic thin quad  
flatpack (TQFP), 119 ball grid array (BGA)  
PinDescriptionSummary  
A0-A19  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Output  
Input  
Input  
I/O  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
N/A  
Chip Enables  
CE1, CE2, CE2  
OE  
Output Enable  
W
R/  
Read/Write Signal  
Clock Enable  
CEN  
Individual Byte Write Selects  
Clock  
BW1, BW2, BW3, BW4  
CLK  
ADV/LD  
Advance burst address / Load new address  
Linear / Interleaved Burst Order  
Test Mode Select  
Test Data Input  
Synchronous  
Static  
LBO  
TMS  
N/A  
TDI  
N/A  
TCK  
Test Clock  
N/A  
TDO  
Test Data Input  
N/A  
JTAG Reset (Optional)  
Sleep Mode  
Asynchronous  
Synchronous  
Synchronous  
Static  
TRST  
ZZ  
I/O0-I/O31, I/OP1-I/OP4  
VDD, VDDQ  
Data Input / Output  
Core Power, I/O Power  
Ground  
Supply  
Supply  
VSS  
Static  
5313 tbl 01  
APRIL 2004  
1
©2004IntegratedDeviceTechnology,Inc.  
DSC-5313/08  

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