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IDT70V06L25JG8 PDF预览

IDT70V06L25JG8

更新时间: 2024-09-17 14:33:59
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
22页 171K
描述
Dual-Port SRAM, 16KX8, 25ns, CMOS, PQCC68, PLASTIC, LCC-68

IDT70V06L25JG8 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:LCC
包装说明:QCCJ,针数:68
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.21
Is Samacsys:N最长访问时间:25 ns
其他特性:INTERRUPT FLAG; SEMAPHORE; AUTOMATIC POWER-DOWNJESD-30 代码:S-PQCC-J68
JESD-609代码:e3长度:24.2062 mm
内存密度:131072 bit内存集成电路类型:DUAL-PORT SRAM
内存宽度:8功能数量:1
端口数量:2端子数量:68
字数:16384 words字数代码:16000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:16KX8
输出特性:3-STATE可输出:YES
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装形状:SQUARE封装形式:CHIP CARRIER
并行/串行:PARALLEL峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:4.57 mm
最小待机电流:2 V最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:MATTE TIN
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:24.2062 mmBase Number Matches:1

IDT70V06L25JG8 数据手册

 浏览型号IDT70V06L25JG8的Datasheet PDF文件第2页浏览型号IDT70V06L25JG8的Datasheet PDF文件第3页浏览型号IDT70V06L25JG8的Datasheet PDF文件第4页浏览型号IDT70V06L25JG8的Datasheet PDF文件第5页浏览型号IDT70V06L25JG8的Datasheet PDF文件第6页浏览型号IDT70V06L25JG8的Datasheet PDF文件第7页 
IDT70V06S/L  
HIGH-SPEED 3.3V  
16K x 8 DUAL-PORT  
STATIC RAM  
Features  
M/S = VIH for BUSY output flag on Master  
M/S = VIL for BUSY input on Slave  
Interrupt Flag  
On-chip port arbitration logic  
Full on-chip hardware support of semaphore signaling  
between ports  
Fully asynchronous operation from either port  
Battery backup operation2V data retention  
TTL-compatible, single 3.3V (±0.3V) power supply  
Available in 68-pin PGA and PLCC, and a 64-pin TQFP  
Industrial temperature range (-40°C to +85°C) is available  
for selected speeds  
True Dual-Ported memory cells which allow simultaneous  
reads of the same memory location  
High-speed access  
– Commercial:15/20/25/35/55ns(max.)  
Industrial:20/25/35/55ns(max.)  
Low-power operation  
IDT70V06S  
Active:400mW(typ.)  
Standby: 3.3mW (typ.)  
IDT70V06L  
Active:380mW(typ.)  
Standby: 660mW (typ.)  
IDT70V06 easily expands data bus width to 16 bits or more  
using the Master/Slave select when cascading more than  
one device  
Functional Block Diagram  
OEL  
OER  
CEL  
CER  
R/WL  
R/WR  
,
I/O0L- I/O7L  
I/O0R-I/O7R  
I/O  
Control  
I/O  
Control  
(1,2)  
BUSYL  
(1,2)  
BUSYR  
A13L  
A13R  
Address  
MEMORY  
ARRAY  
Address  
Decoder  
Decoder  
A0L  
A0R  
14  
14  
ARBITRATION  
INTERRUPT  
SEMAPHORE  
LOGIC  
CEL  
OEL  
CER  
OER  
R/WR  
WL  
R/  
SEML  
INTL  
SEMR  
INTR  
M/S  
(2)  
(2)  
2942 drw 01  
NOTES:  
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.  
2. BUSY outputs and INT outputs are non-tri-stated push-pull.  
MARCH 2000  
1
©2000IntegratedDeviceTechnology,Inc.  
DSC-2942/7  
6.07  

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