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IDT70824L20PF PDF预览

IDT70824L20PF

更新时间: 2024-11-13 22:35:35
品牌 Logo 应用领域
艾迪悌 - IDT 存储
页数 文件大小 规格书
21页 205K
描述
HIGH-SPEED 4K X 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY (SARAM⑩)

IDT70824L20PF 数据手册

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HIGH SPEED 64K (4K X 16 BIT)  
SEQUENTIAL ACCESS  
IDT70824S/L  
RANDOM ACCESS MEMORY (SARAM)  
Features  
High-speed access  
Compatible with Intel BMIC and 82430 PCI Set  
Width and Depth Expandable  
Sequential side  
Address based flags for buffer control  
Military:35/45ns(max.)  
– Commercial:20/25/35/45ns(max.)  
Low-power operation  
IDT70824S  
– Pointer logic supports up to two internal buffers  
Battery backup operation - 2V data retention  
TTL-compatible, single 5V (+10%) power supply  
Available in 80-pin TQFP and 84-pin PGA  
Military product compliant to MIL-PRF-38535 QML  
Industrial temperature range (–40°C to +85°C) is available  
for selected speeds  
Active:775mW(typ.)  
Standby: 5mW (typ.)  
IDT70824L  
Active:775mW(typ.)  
Standby: 1mW (typ.)  
4Kx16SequentialAccess RandomAccess Memory (SARAM )  
– Sequential Access from one port and standard Random  
Access from the other port  
– Separate upper-byte and lower-byte control of the  
RandomAccessPort  
High speed operation  
– 20ns tAA for random access port  
– 20ns tCD for sequential port  
Description  
TheIDT70824isahigh-speed4Kx16-BitSequentialAccessRandom  
AccessMemory(SARAM).TheSARAMoffersasingle-chipsolutionto  
bufferdatasequentiallyononeport,andbeaccessedrandomly(asyn-  
chronously) through the other port. The device has a Dual-Port RAM  
based architecture with a standard SRAM interface for the random  
(asynchronous) access port, and a clocked interface with counter se-  
– 25nsclockcycletime  
Architecture based on Dual-Port RAM cells  
FunctionalBlockDiagram  
12  
RST  
SCLK  
CNTEN  
A0-11  
CE  
OE  
Random  
Sequential  
SOE  
Access  
Access  
SSTRT1  
Port  
R/W  
Port  
Controls  
LB LSB  
UB MSB  
SSTRT2  
Controls  
SCE  
SR/W  
SLD  
4K X 16  
Memory  
Array  
CMD  
16  
16  
16  
DataR  
AddrR  
Reg.  
12  
DataL  
AddrL  
I/O0-15  
SI/O0-15  
,
12  
12  
RST  
12  
Pointer/  
Counter  
12  
12  
Start Address for Buffer #1  
End Address for Buffer #1  
Start Address for Buffer #2  
End Address for Buffer #2  
Flow Control Buffer  
Flag Status  
12  
EOB1  
EOB2  
COMPARATOR  
3099 drw 01  
APRIL 2000  
1
©2000IntegratedDeviceTechnology,Inc.  
DSC-3099/5  
6.07  

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