Datasheet > IDT70824L25GG

IDT70824L25GG

更新时间： 2024-11-15 06:16:51

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器
页数	文件大小	规格书
21页	210K
描述
Standard SRAM, 4KX16, 25ns, CMOS, CPGA84, PGA-84

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中文翻译

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数据手册

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IDT70824L25GG 数据手册

HIGH SPEED 64K (4K X 16 BIT)

SEQUENTIAL ACCESS

IDT70824S/L

RANDOM ACCESS MEMORY (SARAM^™)

Features

◆

High-speed access

Compatible with Intel BMIC and 82430 PCI Set

Width and Depth Expandable

Sequential side

– Address based flags for buffer control

◆

– Military:35/45ns(max.)

◆

– Commercial:20/25/35/45ns(max.)

Low-power operation

◆

– IDT70824S

– Pointer logic supports up to two internal buffers

Battery backup operation - 2V data retention

TTL-compatible, single 5V (+10%) power supply

Available in 80-pin TQFP and 84-pin PGA

Military product compliant to MIL-PRF-38535 QML

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

◆

Active:775mW(typ.)

Standby: 5mW (typ.)

– IDT70824L

◆

Active:775mW(typ.)

Standby: 1mW (typ.)

◆

™

4Kx16SequentialAccess RandomAccess Memory (SARAM )

– Sequential Access from one port and standard Random

Access from the other port

– Separate upper-byte and lower-byte control of the

RandomAccessPort

High speed operation

– 20ns tAA for random access port

– 20ns tCD for sequential port

Description

TheIDT70824isahigh-speed4Kx16-BitSequentialAccessRandom

AccessMemory(SARAM).TheSARAMoffersasingle-chipsolutionto

bufferdatasequentiallyononeport,andbeaccessedrandomly(asyn-

chronously) through the other port. The device has a Dual-Port RAM

based architecture with a standard SRAM interface for the random

(asynchronous) access port, and a clocked interface with counter se-

◆

– 25nsclockcycletime

Architecture based on Dual-Port RAM cells

FunctionalBlockDiagram

RST

SCLK

CNTEN

A0-11

Random

Access

Port

Sequential

SOE

Access

R/W

SSTRT

SCE

SR/W

SLD

Port

Controls

LB ^LSB

Controls

UB ^MSB

CMD

4K X 16

Memory

Array

Data

Reg.

Data

I/O0-15

SI/O0-15

Addr

RST

Pointer/

Counter

Start Address for Buffer #1

End Address for Buffer #1

Start Address for Buffer #2

End Address for Buffer #2

Flow Control Buffer

EOB

COMPARATOR

EOB

Flag Status

3099 drw 01

MAY 2000

DSC-3099/5

6.07

12 3 4 5 6 7...21

中文翻译

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与IDT70824L25GG相关器件

型号	品牌	获取价格	描述	数据表
IDT70824L25GI	IDT	获取价格	HIGH-SPEED 4K X 16 SEQUENTIAL ACCESS RANDOM A
IDT70824L25PF	IDT	获取价格	HIGH-SPEED 4K X 16 SEQUENTIAL ACCESS RANDOM A
IDT70824L25PF8	IDT	获取价格	Standard SRAM, 4KX16, 25ns, CMOS, PQFP80, TQFP-80
IDT70824L25PF9	IDT	获取价格	Standard SRAM, 4KX16, 25ns, CMOS, PQFP80, TQFP-80
IDT70824L25PFB	IDT	获取价格	HIGH-SPEED 4K X 16 SEQUENTIAL ACCESS RANDOM A
IDT70824L25PFG	IDT	获取价格	Standard SRAM, 4KX16, 25ns, CMOS, PQFP80, TQFP-80
IDT70824L25PFG8	IDT	获取价格	Standard SRAM, 4KX16, 25ns, CMOS, PQFP80, TQFP-80
IDT70824L25PFGI	IDT	获取价格	Standard SRAM, 4KX16, 25ns, CMOS, PQFP80, TQFP-80
IDT70824L25PFGI8	IDT	获取价格	Standard SRAM, 4KX16, 25ns, CMOS, PQFP80, TQFP-80
IDT70824L25PFI	IDT	获取价格	HIGH-SPEED 4K X 16 SEQUENTIAL ACCESS RANDOM A

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