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IDT70824L35PF8 PDF预览

IDT70824L35PF8

更新时间: 2024-11-14 14:51:23
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
21页 192K
描述
Standard SRAM, 4KX16, 35ns, CMOS, PQFP80, TQFP-80

IDT70824L35PF8 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:QFP包装说明:TQFP-80
针数:80Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.32.00.41
风险等级:5.91Is Samacsys:N
最长访问时间:35 nsJESD-30 代码:S-PQFP-G80
JESD-609代码:e0长度:14 mm
内存密度:65536 bit内存集成电路类型:STANDARD SRAM
内存宽度:16湿度敏感等级:3
功能数量:1端子数量:80
字数:4096 words字数代码:4000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:4KX16
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装等效代码:QFP80,.64SQ封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE并行/串行:PARALLEL
峰值回流温度(摄氏度):240电源:5 V
认证状态:Not Qualified座面最大高度:1.6 mm
最大待机电流:0.0015 A子类别:Other Memory ICs
最大压摆率:0.29 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:0.65 mm
端子位置:QUAD处于峰值回流温度下的最长时间:20
宽度:14 mmBase Number Matches:1

IDT70824L35PF8 数据手册

 浏览型号IDT70824L35PF8的Datasheet PDF文件第2页浏览型号IDT70824L35PF8的Datasheet PDF文件第3页浏览型号IDT70824L35PF8的Datasheet PDF文件第4页浏览型号IDT70824L35PF8的Datasheet PDF文件第5页浏览型号IDT70824L35PF8的Datasheet PDF文件第6页浏览型号IDT70824L35PF8的Datasheet PDF文件第7页 
HIGH SPEED 64K (4K X 16 BIT)  
SEQUENTIAL ACCESS  
IDT70824S/L  
RANDOM ACCESS MEMORY (SARAM)  
Features  
High-speed access  
Compatible with Intel BMIC and 82430 PCI Set  
Width and Depth Expandable  
Sequential side  
Address based flags for buffer control  
Military:35/45ns(max.)  
– Commercial:20/25/35/45ns(max.)  
Low-power operation  
IDT70824S  
– Pointer logic supports up to two internal buffers  
Battery backup operation - 2V data retention  
TTL-compatible, single 5V (+10%) power supply  
Available in 80-pin TQFP and 84-pin PGA  
Military product compliant to MIL-PRF-38535 QML  
Industrial temperature range (–40°C to +85°C) is available  
for selected speeds  
Active:775mW(typ.)  
Standby: 5mW (typ.)  
IDT70824L  
Active:775mW(typ.)  
Standby: 1mW (typ.)  
4Kx16SequentialAccess RandomAccess Memory (SARAM )  
– Sequential Access from one port and standard Random  
Access from the other port  
– Separate upper-byte and lower-byte control of the  
RandomAccessPort  
High speed operation  
– 20ns tAA for random access port  
– 20ns tCD for sequential port  
Description  
TheIDT70824isahigh-speed4Kx16-BitSequentialAccessRandom  
AccessMemory(SARAM).TheSARAMoffersasingle-chipsolutionto  
bufferdatasequentiallyononeport,andbeaccessedrandomly(asyn-  
chronously) through the other port. The device has a Dual-Port RAM  
based architecture with a standard SRAM interface for the random  
(asynchronous) access port, and a clocked interface with counter se-  
– 25nsclockcycletime  
Architecture based on Dual-Port RAM cells  
FunctionalBlockDiagram  
12  
RST  
SCLK  
CNTEN  
A0-11  
CE  
OE  
Random  
Access  
Port  
Sequential  
SOE  
Access  
R/W  
SSTRT  
SSTRT  
SCE  
SR/W  
SLD  
1
Port  
Controls  
LB LSB  
2
Controls  
UB MSB  
CMD  
4K X 16  
Memory  
Array  
16  
16  
16  
Data  
R
Reg.  
12  
Data  
L
I/O0-15  
SI/O0-15  
,
12  
Addr  
L
Addr  
R
12  
RST  
12  
Pointer/  
Counter  
12  
12  
Start Address for Buffer #1  
End Address for Buffer #1  
Start Address for Buffer #2  
End Address for Buffer #2  
Flow Control Buffer  
12  
EOB  
1
2
COMPARATOR  
EOB  
Flag Status  
3099 drw 01  
JANUARY 2009  
1
©2009IntegratedDeviceTechnology,Inc.  
DSC-3099/6  
6.07  

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