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IDT7052S20PFG8 PDF预览

IDT7052S20PFG8

更新时间: 2024-11-29 14:36:39
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
11页 121K
描述
Four-Port SRAM, 2KX8, 20ns, CMOS, PQFP120, PLASTIC, TQFP-120

IDT7052S20PFG8 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:QFP
包装说明:LFQFP,针数:120
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.21
Is Samacsys:N最长访问时间:20 ns
其他特性:AUTOMATIC POWER-DOWNJESD-30 代码:S-PQFP-G120
JESD-609代码:e3长度:14 mm
内存密度:16384 bit内存集成电路类型:FOUR-PORT SRAM
内存宽度:8湿度敏感等级:3
功能数量:1端子数量:120
字数:2048 words字数代码:2000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:2KX8
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
并行/串行:PARALLEL峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:1.6 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Matte Tin (Sn) - annealed端子形式:GULL WING
端子节距:0.4 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:14 mm
Base Number Matches:1

IDT7052S20PFG8 数据手册

 浏览型号IDT7052S20PFG8的Datasheet PDF文件第2页浏览型号IDT7052S20PFG8的Datasheet PDF文件第3页浏览型号IDT7052S20PFG8的Datasheet PDF文件第4页浏览型号IDT7052S20PFG8的Datasheet PDF文件第5页浏览型号IDT7052S20PFG8的Datasheet PDF文件第6页浏览型号IDT7052S20PFG8的Datasheet PDF文件第7页 
IDT7052S/L  
HIGH-SPEED  
2K x 8 FourPortTM  
STATIC RAM  
Features  
TTL-compatible; single 5V (±10%) power supply  
Available in 120 pin and 132 pin Thin Quad Flatpacks and  
108 pin PGA  
Military product compliant to MIL-PRF-38535 QML  
Industrial temperature range (–40°C to +85°C) is available  
for selected speeds  
High-speed access  
Military:25/35ns(max.)  
– Commercial:20/25/35ns (max.)  
Low-power operation  
IDT7052S  
Active:750mW(typ.)  
Standby: 7.5mW (typ.)  
IDT7052L  
Description  
Active:750mW(typ.)  
Standby: 1.5mW (typ.)  
True FourPort memory cells which allow simultaneous  
TheIDT7052isahigh-speed2Kx8FourPort™StaticRAMdesigned  
to be used in systems where multiple access into a common RAM is  
required.ThisFourPortStaticRAMoffersincreasedsystemperformance  
inmultiprocessorsystemsthathaveaneedtocommunicateinrealtimeand  
alsooffersaddedbenefitforhigh-speedsystemsinwhichmultipleaccess  
is requiredinthe same cycle.  
access of the same memory locations  
Fully asynchronous operation from each of the four ports:  
P1, P2, P3, P4  
Versatile control for write-inhibit: separate BUSY input to  
TheIDT7052is alsodesignedtobeusedinsystems whereon-chip  
hardware port arbitration is not needed. This part lends itself to those  
control write-inhibit for each of the four ports  
Battery backup operation2V data retention  
FunctionalBlockDiagram  
R/WP1  
CEP1  
R/WP4  
CEP4  
OEP1  
OEP4  
COLUMN  
I/O  
COLUMN  
I/O0P1-I/O7P1  
BUSYP1  
I/O0P4-I/O7P4  
I/O  
BUSYP4  
PORT 1  
PORT 4  
ADDRESS  
DECODE  
LOGIC  
ADDRESS  
DECODE  
LOGIC  
A0P1 - A10P1  
A0P4 - A10P4  
MEMORY  
ARRAY  
PORT 2  
ADDRESS  
DECODE  
LOGIC  
PORT 3  
ADDRESS  
DECODE  
LOGIC  
A0P2 - A10P2  
A0P3 - A10P3  
BUSYP2  
BUSYP3  
COLUMN  
I/O  
COLUMN  
I/O  
I/O0P2-I/O7P2  
I/O0P3-I/O7P3  
OEP2  
OEP3  
CEP2  
CEP3  
R/WP3  
R/WP2  
2674 drw 01  
JUNE 1999  
1
DSC 2674/9  
©1999IntegratedDeviceTechnology,Inc.  

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