ICS9248-138
Integrated
Circuit
Systems, Inc.
Preliminary Product Preview
Frequency Generator & Integrated Buffers for Celeron & PII/III™
Recommended Application:
Pin Configuration
810/810E and Solano type chipsetꢀ
1*SEL24_48#/REF0
VDDREF
X1
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDLAPIC
IOAPIC1
Output Features:
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
VDDLCPU
CPUCLK0
CPUCLK1
GNDLCPU
GNDSDR
SDRAM0
SDRAM1
SDRAM2
VDDSDR
SDRAM3
SDRAM4
SDRAM5
GNDSDR
SDRAM6
SDRAM7
SDRAM_F
VDDSDR
GND48
•
•
•
•
•
•
•
•
2- CPUs @ 2.5V
X2
9 - SDRAM @ 3.3V, including 1 free running
7 - PCICLK @ 3.3V
GNDREF
GND3V66
3V66-0
3V66-1
3V66-2
1 - IOAPIC @ 2.5V,
3 - 3V66MHz @ 3.3V
2 - 48MHz, @ 3.3V fixed.
1 - 24/48MHz, @3.3V selectable by I2C
1 - REF @v3.3V, 14.318MHz.
VDD3V66
VDDPCI
1*FS0/PCICLK0
1**FS1/PCICLK1
GNDPCI
PCICLK2
PCICLK3
PCICLK4
VDDPCI
PCICLK5
PCICLK6
GNDPCI
PD#
Features:
•
•
•
Up to 200MHz frequency support
Support FS0-FS4 strapping status bit for I2C read back.
Support power management: Through Power down
Mode from I2C programming.
24_48MHz/FS2**
48MHz/FS3*
48MHz/FS4*1
VDD48
•
•
Spread spectrum for EMI control ( ± 0.25% center).
Uses external 14.318MHz crystal
SCLK
SDATA
Skew Specifications:
•
•
•
•
•
CPU – CPU: <175ps
48-Pin 300mil SSOP
* These inputs have a 120K pull up to VDDꢀ
** These inputs have a 120K pull down to GNDꢀ
1 These are double strengthꢀ
SDRAM - SDRAM: < 250ps
3V66 – 3V66: <175ps
PCI – PCI: <500ps
For group skew specifications, please refer to group
timing relationship.
Functionality
CPU
(MHz)
66.67
66.87
68.67
SDRAM
(MHz)
100.00
100.30
103.00
107.00
100.00
100.30
103.00
107.00
133.33
133.73
137.33
120.00
100.00
100.30
103.00
90.00
3V66
(MHz)
66.67
66.87
68.67
71.34
66.67
66.87
68.67
71.34
66.67
66.87
68.67
60.00
66.67
66.87
68.67
60.00
PCICLK
(MHz)
33.33
33.43
34.33
35.66
33.33
33.43
34.33
35.66
33.33
33.43
34.33
30.00
33.33
33.43
34.33
30.00
IOAPIC
(MHz)
16.67
16.72
17.16
17.83
16.67
16.72
17.17
17.84
16.67
16.72
17.17
15.00
16.67
16.72
17.17
15.00
FS4 FS3 FS2 FS1 FS0
Block Diagram
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
PLL2
48MHz [1:0]
24_48MHz
2
71.34
/ 2
100.00
100.30
103.00
107.00
133.33
133.73
137.33
120.00
133.33
133.73
137.33
120.00
X1
X2
XTAL
OSC
REF0
PLL1
Spread
Spectrum
CPU
DIVDER
CPUCLK [1:0]
2
8
SDRAM
DIVDER
SDRAM [7:0]
SDRAM_F
IOAPIC
SEL24_48#
IOAPIC
DIVDER
Control
Logic
SDATA
SCLK
PCI
DIVDER
PCICLK [6:0]
3V66 [2:0]
7
FS[4:0]
PD#
1
1
1
1
1
1
1
1
0
1
0
1
1
0
1
1
0
1
1
0
160.00
160.00
166.67
166.67
160.00
120.00
166.67
125.00
80.00
80.00
83.34
83.34
40.00
40.00
41.67
41.67
20.00
20.00
20.84
20.84
Config.
Reg.
3V66
DIVDER
3
Additional frequencies selectable through I2C programmingꢀ
PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.
9248- 138 Rev A 10/03/00
Third party brands and names are the property of their respective owners.