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ICS9248YF-141LF-T PDF预览

ICS9248YF-141LF-T

更新时间: 2024-11-13 21:13:55
品牌 Logo 应用领域
艾迪悌 - IDT 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
14页 155K
描述
Processor Specific Clock Generator, 166.66MHz, PDSO48, 0.300 INCH, SSOP-48

ICS9248YF-141LF-T 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SSOP
包装说明:SSOP,针数:48
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.28
JESD-30 代码:R-PDSO-G48JESD-609代码:e3
长度:15.875 mm端子数量:48
最高工作温度:70 °C最低工作温度:
最大输出时钟频率:166.66 MHz封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH峰值回流温度(摄氏度):260
主时钟/晶体标称频率:16 MHz认证状态:Not Qualified
座面最大高度:2.794 mm最大供电电压:3.465 V
最小供电电压:3.135 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:MATTE TIN
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:7.5 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches:1

ICS9248YF-141LF-T 数据手册

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Integrated  
Circuit  
Systems, Inc.  
ICS9248-141  
AMD - K7System Clock Chip  
Recommended Application:  
VIA KX133 style chipset  
Output Features:  
Pin Configuration  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
VDDREF  
REF0/CPU_STOP#*  
GND  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
REF1/FS2*  
GND  
CPUCLKT1  
GND  
CPUCLKC0  
CPUCLKT0  
VDDA  
PD#*  
SDRAM_OUT  
GND  
SDRAM0  
SDRAM1  
VDDSDR  
SDRAM2  
SDRAM3  
GND  
SDRAM4  
SDRAM5  
VDDSDR  
SDRAM6  
SDRAM7  
VDD48  
1 - Differential pair open drain CPU clocks  
1 - Single-ended open drain CPU clock  
13 - SDRAM @ 3.3V  
6 - PCI @3.3V,  
1 - 48MHz, @3.3V fixed.  
X1  
X2  
VDDPCI  
*MODE/PCICLK_F  
*FS3/PCICLK0  
GND  
1 - 24/48MHz @ 3.3V  
2 - REF @3.3V, 14.318MHz.  
*SEL24_48#/PCICLK1  
PCICLK2  
PCICLK3  
PCICLK4  
VDDPCI  
Features:  
Up to 166MHz frequency support  
BUFFER IN  
GND  
Support power management: CPU stop and Power down  
Mode from I2C programming.  
SDRAM11  
SDRAM10  
VDDSDR  
SDRAM9  
SDRAM8  
GND  
Spread spectrum for EMI control  
(
ꢀ.2ꢁ5 center spreadꢂ.  
Uses external 14.318MHz crystal  
SDATA  
SCLK  
48MHz/FS0*  
24/48MHz/FS1*  
48-Pin 300mil SSOP  
*
Internal Pull-up Resistor of 120K to VDD  
Functionality  
Block Diagram  
CPU  
(MHz)  
90.00  
PCICLK  
(MHz)  
30.00  
31.67  
33.67  
34.00  
33.57  
34.33  
35.00  
33.33  
35.67  
36.33  
36.67  
37.00  
37.67  
38.33  
39.00  
33.33  
PLL2  
48MHz  
FS3  
FS2  
FS1  
FS0  
24_48MHz  
/ 2  
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
95.00  
X1  
X2  
XTAL  
OSC  
REF (1:0)  
101.00  
102.00  
100.90  
103.00  
105.00  
100.00  
107.00  
109.00  
110.00  
111.00  
113.00  
115.00  
117.00  
133.30  
PLL1  
Spread  
Spectrum  
CPU  
DIVDER  
Stop  
CPUCLKC0  
CPUCLKT (1:0)  
SEL24_48#  
PCI  
DIVDER  
PCICLK (4:0)  
PCICLK_F  
Control  
Logic  
SDATA  
SCLK  
FS (3:0)  
Config.  
Reg.  
SDRAM  
DRIVER  
SDRAM (11:0)  
SDRAM_OUT  
PD#  
CPU_STOP#  
BUFFER IN  
ICS reserves the right to make changes in the device data  
identified in this publication without further notice. ICS advises  
its customers to obtain the latest version of all device data to  
verify that any information being relied upon by the customer is  
9248-141 Rev B 01/18/01  
Third party brands and names are the property of their respective owners.  

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