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ICS9248YF-168-T PDF预览

ICS9248YF-168-T

更新时间: 2024-09-24 22:15:35
品牌 Logo 应用领域
矽成 - ICSI 时钟发生器移动系统
页数 文件大小 规格书
14页 173K
描述
AMD - K7⑩ Clock Generator for Mobile System

ICS9248YF-168-T 数据手册

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Integrated  
Circuit  
Systems, Inc.  
ICS9248-168  
AMD - K7Clock Generator for Mobile System  
Recommended Application:  
VIA KT133 style chipset  
Pin Configuration  
Output Features:  
48  
VDDREF  
X1  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
REF01  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
REF  
1
1 - Differential pair open drain CPU clocks  
1 - CPU clock @ 3.3V  
7 - SDRAM @ 3.3V  
8 - PCI @ 3.3V,  
1 - 48MHz, @ 3.3V fixed.  
1 - 24/48MHz @ 3.3V  
X2  
REF2  
GND  
GND  
VDD  
*FS2/PCICLK_F  
*FS1/PCICLK0  
VDDPCI  
GND  
PCICLK1  
PCICLK2  
PCICLK3  
PCICLK4  
PCICLK5  
GND  
VDDPCI  
CPUCLK2  
CPUCLKT02  
CPUCLKC02  
CPU_STOP#*  
PD#*  
3 - REF @ 3.3V, 14.318MHz.  
SDRAM0  
SDRAM1  
VDDSDR  
GND  
SDRAM2  
SDRAM3  
GND  
VDDSDR  
SDRAM4  
SDRAM5  
SDRAM_F  
SCLK  
Features:  
Up to 153MHz frequency support  
PCICLK6  
Support power management: CPU stop and Power down  
Mode from I2C programming.  
*SDRAM_STOP#  
*PCI_STOP#  
BUFFER_IN  
AVDD  
Spread spectrum for EMI control  
(
ꢀ.25ꢁ to ꢀ.0ꢁ center, or ꢀ to -ꢀ.5ꢁ or -1.ꢀꢁ down  
GND  
GND  
spread).  
Uses external 14.318MHz crystal  
*FS0/48MHZ  
*SEL24_48#/24_48MHz  
VDD48  
SDATA  
48-Pin 300mil SSOP  
*
Internal Pull-up Resistor of 120K to VDD  
1
These outputs have double strength to drive 2 loads.  
These outputs can be set to 1.5X strength through I2C  
2
Functionality  
Block Diagram  
FS2  
0
FS1  
0
FS0  
0
CPU  
PCI  
33.33  
33.33  
Spread Percentage  
+/- 0.35% Center Spread  
+/- 0.35% Center Spread  
PLL2  
48MHz  
100.00  
133.33  
100.00  
133.33  
100.00  
133.33  
90.00  
24_48MHz  
0
0
1
/ 2  
0
1
0
33.33 0 to - 0.5% Down Spread  
33.33 0 to - 0.5% Down Spread  
REF (2:0)  
CPUCLK  
X1  
X2  
XTAL  
OSC  
0
1
1
1
0
0
33.33  
33.33  
30.00  
30.00  
+/- 0.6% Center Spread  
+/- 0.6% Center Spread  
+/- 0.25% Center Spread  
+/- 0.25% Center Spread  
PLL1  
Spread  
Spectrum  
CPU  
DIVDER  
1
0
1
Stop  
CPUCLKC0  
CPUCLKT0  
1
1
0
1
1
1
120.00  
SEL24_48#  
SDATA  
PCI  
DIVDER  
Stop  
Stop  
PCICLK (6:0)  
PCICLK_F  
Control  
Logic  
SCLK  
FS (2:0)  
SDRAM  
DRIVER  
PD#  
SDRAM (5:0)  
SDRAM_F  
CPU_STOP#  
PCI_STOP#  
SDRAM_STOP#  
BUFFER_IN  
Config.  
Reg.  
ICS reserves the right to make changes in the device data identified in  
this publication without further notice. ICS advises its customers to  
obtain the latest version of all device data to verify that any  
9248-168 Rev  
B 01/09/01  
Third party brands and names are the property of their respective owners.  
information being relied upon by the customer is current and accurate.  

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