Datasheet > ICS9248YF-39

ICS9248YF-39

更新时间： 2024-09-24 22:25:15

品牌	Logo	应用领域
矽成 - ICSI		晶体外围集成电路光电二极管时钟
页数	文件大小	规格书
16页	293K
描述
Frequency Generator & Integrated Buffers for PENTIUM/ProTM

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数据手册

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ICS9248YF-39 数据手册

Integrated

Circuit

Systems, Inc.

ICS9248-39

Frequency Generator & Integrated Buffers for PENTIUM/Pro^TM

General Description

Features

•

3.3V outputs: SDRAM, PCI, REF, 48/24MHz

The ICS9248-39 generates all clocks required for high speed

RISC or CISC microprocessor systems such as Intel

PentiumPro or Cyrix. Eight different reference frequency

multiplying factors are externally selectable with smooth

frequency transitions.

2.5V outputs: CPU, IOAPIC

20 ohm CPU clock output impedance

20 ohm PCI clock output impedance

Skew from CPU (earlier) to PCI clock - 1.5 to 4 ns,

center 2.6 ns.

•

No external load cap for C_L=18pF crystals

±175 ps CPU clock skew

Features include two CPU, six PCI and thirteen SDRAM

clocks. Two reference outputs are available equal to the crystal

frequency. Plus the IOAPIC output powered by VDDL1. One

48 MHz for USB, and one 24 MHz clock for Super IO. Spread

Spectrum built in at ±0.5% or ±0.25% modulation to reduce

the EMI. Serial programming I²C interface allows changing

functions, stop clock programing and Frequency selection.

Additionally, the device meets the Pentium power-up

stabilization, which requires that CPU and PCI clocks be

stable within 2ms after power-up. It is not recommended to

use I/O dual function pin for the slots (ISA, PIC, CPU,

DIMM). The add on card might have a pull up or pull down.

250ps (cycle to cycle) CPU jitter

Smooth frequency switch, with selections from 66.8

to 150 MHz CPU.

•

I²C interface for programming

3ms power up clock stable time

Clock duty cycle 45-55%.

48 pin 300 mil SSOP package

3.3V operation, 5V tolerant inputs (with series R)

<5ns propagation delay SDRAM from Buffer Input

Pin Configuration

High drive PCICLK and SDRAM outputs typically provide

greater than 1 V/ns slew rate into 30pF loads. CPUCLK

outputs typically provide better than 1V/ns slew rate into 20pF

loads while maintaining 50±5% duty cycle. The REF and 24

and 48 MHz clock outputs typically provide better than 0.5V/

ns slew rates into 20pF.

Block Diagram

48-Pin SSOP

* Internal Pull-up Resistor of 240K to VDD

** Internal Pull-down resistor of 240K to GND

Power Groups

VDD1 = REF (0:1), X1, X2

VDD2 = PCICLK_F, PCICLK(0:4)

VDD3 = SDRAM (0:12), supply for PLL core

VDD4 = 24MHz, 48MHz

VDDL1 = IOAPIC

VDDL2 = CPUCLK 1, CPUCLK_F

Pentium is a trademark of Intel Corporation

I²C is a trademark of Philips Corporation

ICS reserves the right to make changes in the device data identified in

this publication without further notice. ICS advises its customers to

obtain the latest version of all device data to verify that any

9248-39RevF12/16/99

information being relied upon by the customer is current and accurate.

12 3 4 5 6 7...16

中文翻译

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与ICS9248YF-39相关器件

型号	品牌	获取价格	描述	数据表
ICS9248YF-39LF-T	IDT	获取价格	Processor Specific Clock Generator, 150MHz, PDSO48, 0.300 INCH, LEAD FREE, SSOP-48
ICS9248YF-39-T	IDT	获取价格	Processor Specific Clock Generator, 150MHz, PDSO48, 0.300 INCH, SSOP-48
ICS9248YF-50	IDT	获取价格	Processor Specific Clock Generator, 100MHz, PDSO28, 0.209 INCH, SSOP-28
ICS9248YF-50LF	IDT	获取价格	Processor Specific Clock Generator, 100MHz, PDSO28, 0.209 INCH, SSOP-28
ICS9248YF-50LF-T	IDT	获取价格	Processor Specific Clock Generator, 100MHz, PDSO28, 0.209 INCH, MO-150, SSOP-28
ICS9248YF-64	ICSI	获取价格	AMD-K7TM System Clock Chip
ICS9248YF-65	ICSI	获取价格	Frequency Timing Generator for PENDIUM II Systems
ICS9248YF-66	ICSI	获取价格	Frequency Timing Generator for PENTIUM II Systems
ICS9248YF-66	IDT	获取价格	Processor Specific Clock Generator, 133.3MHz, PDSO48, SSOP-48
ICS9248YF-66LF	IDT	获取价格	Processor Specific Clock Generator, 133.3MHz, PDSO48, SSOP-48

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