Datasheet > ICS9248YF-90-T

ICS9248YF-90-T

更新时间： 2024-09-24 22:31:39

品牌	Logo	应用领域
矽成 - ICSI		/
页数	文件大小	规格书
16页	283K
描述
Frequency Generator & Integrated Buffers for PENTIUM/ProTM

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数据手册

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ICS9248YF-90-T 数据手册

Integrated

Circuit

Systems, Inc.

ICS9248-90

Frequency Generator & Integrated Buffers for PENTIUM/Pro^TM

General Description

Features

•

3.3V outputs: SDRAM, PCI, REF, 48/24MHz

The ICS9248-90 generates all clocks required for high speed

RISC or CISC microprocessor systems such as Intel

PentiumPro or Cyrix. Eight different reference frequency

multiplying factors are externally selectable with smooth

frequency transitions.

2.5V outputs: CPU, IOAPIC

20 ohm CPU clock output impedance

20 ohm PCI clock output impedance

Skew from CPU (earlier) to PCI clock - 1.5 to 4 ns,

center 2.6 ns.

•

No external load cap for C_L=18pF crystals

±175 ps CPU clock skew

Features include two CPU, six PCI and thirteen SDRAM

clocks. Two reference outputs are available equal to the crystal

frequency. Plus the IOAPIC output powered by VDDL1. One

48 MHz for USB, and one 24 MHz clock for Super IO. Spread

Spectrum built in at ±0.25% modulation to reduce the EMI.

Serial programming I²C interface allows changing functions,

stop clock programing and Frequency selection.Additionally,

the device meets the Pentium power-up stabilization, which

requires that CPU and PCI clocks be stable within 2ms after

power-up. It is not recommended to use I/O dual function pin

for the slots (ISA, PIC, CPU, DIMM). The add on card might

have a pull up or pull down.

250ps (cycle to cycle) CPU jitter

Smooth frequency switch, with selections from 66.8

to 133 MHz CPU.

•

I²C interface for programming

3ms power up clock stable time

Clock duty cycle 45-55%.

48 pin 300 mil SSOP package

3.3V operation, 5V tolerant inputs (with series R)

<5ns propagation delay SDRAM from Buffer Input

Pin Configuration

High drive PCICLK and SDRAM outputs typically provide

greaterthan1V/nsslewrateinto30pFloads. CPUCLKoutputs

typically provide better than 1V/ns slew rate into 20pF loads

while maintaining 50 ±5% duty cycle. The REF and 24 and

48 MHz clock outputs typically provide better than 0.5V/ns

slew rates into 20pF.

Block Diagram

PLL2

48MHz

24MHz

XTAL

OSC

48-Pin SSOP

STOP

IOAPIC

* Internal Pull-up Resistor of 240K to VDD

** Internal Pull-down resistor of 240K to GND

BUFFER IN

REF(0:1)

CPUCLK_F

CPUCLK 1

PLL1

Spread

Spectrum

STOP

Power Groups

VDDREF = REF (0:1), X1, X2

VDDPCI=PCICLK_F, PCICLK(0:4)

VDDSDR = SDRAM (0:12), supply for PLL core

VDD48 = 24MHz, 48MHz

FS(0:3)

MODE

SDRAM (0:11)

SDRAM_F

LATCH

POR

PCI

CLOCK

DIVDER

CPU_STOP#

PCI_STOP#

STOP

PCICLK (0:4)

PCICLKF

VDDLIOAPIC=IOAPIC

VDDLCPU=CPUCLK1, CPUCLK_F

Control

Logic

SDATA

SCLK

Config.

Reg.

Pentium is a trademark of Intel Corporation

I²C is a trademark of Philips Corporation

ICS reserves the right to make changes in the device data identified in

this publication without further notice. ICS advises its customers to

obtain the latest version of all device data to verify that any

9248-90RevC4/19/00

information being relied upon by the customer is current and accurate.

12 3 4 5 6 7...16

中文翻译

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ICS9248YG-143-T	IDT	获取价格	Processor Specific Clock Generator, 133.37MHz, PDSO48, 6.10 MM, 0.50 MM PITCH, TSSOP-48
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