ICS9220
Integrated
Circuit
Systems, Inc.
Programmable RambusTM XDRTM Clock Generator
General Description
Features
•
•
300 - 700 MHz clock source
2 open-drain differential output drives with short
term jitter < 40ps
Spread spectrum compatible
Reference clock is differential or single-ended
100MHz
SMBus programmability for:
- frequency multiplier
- output enable
- operating mode
Support systems where XDR subsystem is
asynchronous to other system clocks
The ICS9220 clock generator provides Programmable
clock signals to support the Rambus XDRTM memory
subsystem and Redwood logic interface. The ICS9220
has been optimized for 100MHz reference input that may
or may not be modulated for spread spectrum. The
ICS9220 provides 2 differential clock pairs in a space
saving 28-pin TSSOP package and provides an off-the-
shelf high-performance interface solution.
•
•
•
Figure 1 shows the major components of the ICS9220
XDR Clock Generator. These include the a PLL, a Bypass
Multiplexer and two differential output buffers. The outputs
can be disabled by a logic low on the OE pin. An output
is enabled by the combination of the OE pin being high,
and 1 in its SMBus Output control register bit.
•
•
2.5V power supply
The PLL receives a reference clock, CLK_INT/C and
outputs a clock signal at a frequency equal to the input
frequency times a multiplier. Table 2 shows the multipliers
selectable via the SMBus interface. This clock signal is
then fed to the differential output buffers to drive the
enabled clocks. Disabled outputs are set to Hi-Z. The
Bypass mode routes the input clock, CLK_INT/C, directly
to the differential output buffers, bypassing the PLL.
Up to four ICS9220 devices can be cascaded on the same
SMBus. Table 3 shows the SMBus addressing and control
for the four devices.
Block Diagram
Pin Configuration
OE
AVDD2.5
AGND
1
2
3
4
5
6
7
8
9
28 VDD2.5
27 GND
26 GND
25 ODCLK_T0
24 ODCLK_C0
23 GND
22 VDD2.5
21 VDD2.5
20 GND
OE
RegA
IREFY
AGND
CLK_INT
CLK_INC
VDD2.5
GND
SMBCLK
SMBDAT 10
OE 11
ODCLK_T0
BYPASS#/PLL
ODCLK_C0
Bypass
MUX
OE
RegB
ODCLK_T1
ODCLK_C1
CLK_INT
CLK_INC
PLL
SMBCLK
19 ODCLK_T1
18 ODCLK_C1
17 GND
SMBDAT
AS1
AS2
AS1 12
AS2 13
16 GND
BYPASS#/PLL 14
15 VDD2.5
28-Pin 4.4mm TSSOP
1227G—11/05/07
XDR is a trademark of Rambus