Datasheet > ICS9220B

ICS9220B

更新时间： 2024-09-29 05:39:03

品牌	Logo	应用领域
艾迪悌 - IDT		时钟发生器
页数	文件大小	规格书
16页	187K
描述
Programmable RambusTM XDRTM Clock Generator

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中文翻译

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ICS9220B 数据手册

DATASHEET

Programmable Rambus^TMXDR^TMClock Generator

ICS9220B

General Description

Features

The ICS9220 clock generator provides Programmable clock • 300 - 700 MHz clock source

signals to support the Rambus XDR^TMmemory subsystem

•

2 open-drain differential output drives with short

and Redwood logic interface. The ICS9220 has been

optimized for 100MHz reference input that may or may not be

modulated for spread spectrum. The ICS9220 provides 2

differential clock pairs in a space saving 28-pin TSSOP

package and provides an off-the-shelf high-performance

interface solution.

term jitter < 40ps

•

Spread spectrum compatible

Reference clock is differential or single-ended

100MHz

SMBus programmability for:

- frequency multiplier

- output enable

- operating mode

Support systems where XDR subsystem is

asynchronous to other system clocks

•

Figure 1 shows the major components of the ICS9220 XDR

Clock Generator. These include the a PLL, a Bypass

Multiplexer and two differential output buffers. The outputs

can be disabled by a logic low on the OE pin. An output is

enabled by the combination of the OE pin being high, and 1

in its SMBus Output control register bit.

•

2.5V power supply

The PLL receives a reference clock, CLK_INT/C and outputs

a clock signal at a frequency equal to the input frequency

times a multiplier. Table 2 shows the multipliers selectable

via the SMBus interface. This clock signal is then fed to the

differentialoutputbufferstodrivetheenabledclocks. Disabled

outputs are set to Hi-Z. The Bypass mode routes the input

clock, CLK_INT/C, directly to the differential output buffers,

bypassing the PLL.

Up to four ICS9220 devices can be cascaded on the same

SMBus.Table 3 shows the SMBus addressing and control for

the four devices.

Block Diagram

Pin Configuration

AVDD2.5

AGND

28 VDD2.5

27 GND

26 GND

25 ODCLK_T0

24 ODCLK_C0

23 GND

22 VDD2.5

21 VDD2.5

20 GND

IREFY

AGND

CLK_INT

CLK_INC

VDD2.5

GND

SMBCLK

SMBDAT 10

OE 11

RegA

ODCLK_T0

BYPASS#/PLL

ODCLK_C0

Bypass

MUX

RegB

ODCLK_T1

ODCLK_C1

CLK_INT

CLK_INC

19 ODCLK_T1

18 ODCLK_C1

17 GND

PLL

SMBCLK

AS1 12

AS2 13

16 GND

BYPASS#/PLL 14

15 VDD2.5

SMBDAT

AS1

AS2

28-Pin 4.4mm TSSOP

IDT^TMProgrammable Rambus^TMXDR^TMClock Generator

1427A—01/26/10

12 3 4 5 6 7...16

中文翻译

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与ICS9220B相关器件

型号	品牌	获取价格	描述	数据表
ICS9220YGLF-T	IDT	获取价格	Processor Specific Clock Generator, PDSO28, 4.40 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-153
ICS9222-01	ICSI	获取价格	Dual Memory Clock Generator
ICS9222-01	IDT	获取价格	Dual Memory Clock Generator
ICS9222G-01LF-T	IDT	获取价格	Clock Driver, PDSO28
ICS9222G-01-T	IDT	获取价格	Clock Driver, PDSO28
ICS9222-YG01LF-T	IDT	获取价格	PLL Based Clock Driver, 9222 Series, 2 True Output(s), 2 Inverted Output(s), PDSO28, 4.40
ICS9222YG-01LF-T	IDT	获取价格	PLL Based Clock Driver, 9222 Series, 2 True Output(s), 2 Inverted Output(s), PDSO28, 4.40
ICS9222YG-01-T	IDT	获取价格	PLL Based Clock Driver, 9222 Series, 2 True Output(s), 2 Inverted Output(s), PDSO28, 4.40
ICS9248-101	ICSI	获取价格	Frequency Generator & Integrated Buffers for PENTIUM/ProTM & K6
ICS9248-103	ICSI	获取价格	Frequency Generator & Integrated Buffers for PENTIUM/ProTM

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