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ICS87158AGAFT PDF预览

ICS87158AGAFT

更新时间: 2024-11-16 19:59:55
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
16页 242K
描述
Prescaler/Multivibrator

ICS87158AGAFT 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
Reach Compliance Code:not_compliant风险等级:5.92
Base Number Matches:1

ICS87158AGAFT 数据手册

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ICS87158  
1-TO-6, LVPECL-TO-HCSL/LVCMOS  
÷1, ÷2, ÷4 CLOCK GENERATOR  
Integrated  
Circuit  
Systems, Inc.  
GENERAL DESCRIPTION  
FEATURES  
The ICS87158 is a high performance 1-to-6 Six HCSL outputs  
ICS  
HiPerClockS™  
LVPECL-to-HCSL/LVCMOS Clock Generator  
Two LVCMOS/LVTTL outputs  
and is a member of the HiPerClockS™ family of  
High Performance Clock Solutions from ICS.The  
ICS87158 has one differential input (which can  
One Differential LVPECL clock input pair  
PCLK, nPCLK supports the following input types:  
LVDS, LVPECL, LVHSTL, SSTL, HCSL  
accept LVDS, LVPECL, LVHSTL, SSTL, HCSL), six differential  
HCSL output pairs and two complementary LVCMOS/LVTTL  
outputs. The six HCSL output pairs can be individually con-  
figured for divide-by-1, 2, and 4 or high impedance by use of  
select pins. The two complementary LVCMOS/LVTTL outputs  
can be configured for divide by 2, divide by 4, high imped-  
ance, or driven low for low power operation.  
Maximum output frequency: 600MHz (maximum)  
Output skew: 100ps (maximum)  
Propagation delay: 4ns (maximum)  
3.3V operating supply  
®
The primary use of the ICS87158 is in Intel E8870 chipsets  
0°C to 85°C ambient operating temperature  
®
that use Intel Pentium 4 processors. The ICS87158 converts  
the differential clock from the main system clock into HCSL  
clocks used by Intel Pentium 4 processors. However, the  
Available in both standard and lead-free RoHS compliant  
packages  
®
ICS87158 is a highly flexible, general purpose device that  
operates up to 600MHz and can be used in any situation where  
Differential-to-HCSL translation is required.  
Industrial temperature information available upon request  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
GND  
VDD  
VDD_R  
PCLK  
nPCLK  
GND_R  
VDD_M  
MREF  
nMREF  
GND_M  
VDD  
GND  
VDD_L  
VDD  
GND_L  
SEL_T  
MULT_0  
MULT_1  
VDD_L  
1
2
3
4
5
6
7
8
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
VDD  
GND_H  
VDD_H  
MULT_0  
CURRENT  
MULT_1  
ADJUST  
VDD  
HOST_P1  
HOST_N1  
GND_H  
HOST_P2  
HOST_N2  
VDD_H  
HOST_P3  
HOST_N3  
GND_H  
HOST_P4  
HOST_N4  
VDD_H  
HOST_P5  
HOST_N5  
GND_H  
HOST_P6  
HOST_N6  
VDD_H  
IREF  
-
HOST_P1  
HOST_N1  
GND_H  
VDD  
+
÷1,2,4  
PWR_DWN#  
SEL_T  
9
HOST_P6  
HOST_N6  
GND_H  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
VDD  
HOST_P2  
HOST_N2  
GND_H  
VDD  
÷1,2,4  
PCLK  
nPCLK  
HOST_P3  
GND_L  
SEL_A  
SEL_B  
SEL_U  
PWR_DWN#  
HOST_N3  
GND_H  
VDD  
IREF  
GND_I  
VDD_I  
HOST_P4  
HOST_N4  
GND_H  
VDD  
48-LeadTSSOP  
6.1mm x 12.5mm x .92mm body package  
HOST_P5  
HOST_N5  
GND_H  
G Package  
TopView  
SEL_A  
SEL_B  
SEL_U  
DIVIDER  
CONTROL  
VDD  
48-Lead SSOP  
7.5mm x 15.9mm x 2.3mm body package  
F Package  
MREF  
nMREF  
GND_H  
÷2,4  
TopView  
87158AG  
www.icst.com/products/hiperclocks.html  
REV.B MARCH 10, 2006  
1

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