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ICS8725AY-01LFT PDF预览

ICS8725AY-01LFT

更新时间: 2024-11-16 19:45:51
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
16页 229K
描述
PLL Based Clock Driver, 8725 Series, 5 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-026, LQFP-32

ICS8725AY-01LFT 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:End Of Life零件包装代码:QFP
包装说明:7 X 7 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-026, LQFP-32针数:32
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.19系列:8725
输入调节:DIFFERENTIAL MUXJESD-30 代码:S-PQFP-G32
JESD-609代码:e3长度:7 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER湿度敏感等级:3
功能数量:1反相输出次数:
端子数量:32实输出次数:5
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装等效代码:QFP32,.35SQ,32封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE峰值回流温度(摄氏度):260
电源:3.3 VProp。Delay @ Nom-Sup:4.4 ns
传播延迟(tpd):4.4 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.025 ns座面最大高度:1.6 mm
子类别:Clock Drivers最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:COMMERCIAL
端子面层:Matte Tin (Sn) - annealed端子形式:GULL WING
端子节距:0.8 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:7 mm
最小 fmax:31.25 MHzBase Number Matches:1

ICS8725AY-01LFT 数据手册

 浏览型号ICS8725AY-01LFT的Datasheet PDF文件第2页浏览型号ICS8725AY-01LFT的Datasheet PDF文件第3页浏览型号ICS8725AY-01LFT的Datasheet PDF文件第4页浏览型号ICS8725AY-01LFT的Datasheet PDF文件第5页浏览型号ICS8725AY-01LFT的Datasheet PDF文件第6页浏览型号ICS8725AY-01LFT的Datasheet PDF文件第7页 
ICS8725-01  
1:5 DIFFERENTIAL-TO-HSTL  
ZERO DELAY CLOCK GENERATOR  
Integrated  
Circuit  
Systems, Inc.  
GENERAL DESCRIPTION  
FEATURES  
The ICS8725-01 is a highly versatile 1:5 Dif- Five differential HSTL outputs  
ICS  
HiPerClockS™  
ferential-to-HSTL clock generator and a  
Selectable differential CLKx, nCLKx input pairs  
member of the HiPerClockS™ family of High  
Performance Clock Solutions from ICS. The  
ICS8725-01 has a fully integrated PLL and can  
CLKx, nCLKx pairs can accept the following differential  
input levels: LVPECL, LVDS, HSTL, SSTL, HCSL  
be configured as zero delay buffer, multiplier or divider,  
and has an output frequency range of 31.25MHz to  
700MHz. The reference divider, feedback divider and out-  
put divider are each programmable, thereby allowing for  
the following output-to-input frequency ratios: 8:1, 4:1, 2:1,  
1:1, 1:2, 1:4, 1:8. The external feedback allows the device  
to achieve “zero delay” between the input clock and the  
output clocks. The PLL_SEL pin can be used to bypass the  
PLL for system test and debug purposes. In bypass mode,  
the reference clock is routed around the PLL and into the  
internal output dividers.  
Output frequency range: 31.25MHz to 700MHz  
Input frequency range: 31.25MHz to 700MHz  
VCO range: 250MHz to 700MHz  
External feedback for “zero delay” clock regeneration  
with configurable frequencies  
Programmable dividers allow for the following output-to-input  
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8  
Static phase offset: 100ps  
Cycle-to-cycle jitter: 25ps  
Output skew: 25ps  
3.3V core, 1.8V output operating supply  
0°C to 70°C ambient operating temperature  
Available in both standard and lead-free RoHS-compliant  
packages  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
PLL_SEL  
Q0  
nQ0  
Q1  
nQ1  
÷1, ÷2, ÷4, ÷8,  
÷16, ÷32,÷64  
32 31 30 29 28 27 26 25  
0
1
CLK0  
nCLK0  
Q2  
nQ2  
0
1
1
2
3
4
5
6
7
8
24  
23  
22  
21  
20  
19  
18  
17  
SEL0  
SEL1  
VDDO  
Q3  
CLK1  
nCLK1  
Q3  
nQ3  
CLK0  
nQ3  
Q2  
PLL  
nCLK0  
CLK1  
Q4  
nQ4  
ICS8725-01  
10 11 12 13 14 15 16  
32-Lead LQFP  
CLK_SEL  
nQ2  
Q1  
8:1, 4:1, 2:1, 1:1,  
1:2, 1:4, 1:8  
nCLK1  
CLK_SEL  
FB_IN  
nFB_IN  
nQ1  
VDDO  
MR  
9
SEL0  
SEL1  
SEL2  
SEL3  
MR  
7mm x 7mm x 1.4mm package body  
Y Package  
TopView  
8725AY-01  
www.icst.com/products/hiperclocks.html  
REV.B NOVEMBER 15, 2005  
1

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